Senior RTL2GDS Methodology Architect (Equity Eligible)

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 168,000 - 265,000; Full time

Benefits offered by this job

Equity and benefits package

Competitive compensation

Job summary

NVIDIA is seeking an experienced ASIC Implementation Engineer in Santa Clara to own the RTL2GDS methodology for advanced CPU builds. You will evaluate EDA tools, define standards, and lead automation efforts to boost PPA across the design cycle.

Responsibilities include driving flow optimization, conducting QoR experiments, and collaborating with architecture, RTL, DFT, and physical teams to maximize silicon performance. The role emphasizes scripting, data-driven analysis, and vendor interaction.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent experience.
• 6+ years of hands-on proven experience in ASIC implementation methodology and EDA tool/flow development.
• Deep, practical expertise in the complete RTL2GDS flow: synthesis, DFT, floorplanning, placement, CTS, routing, and MCMM STA.
• EDA Tool Proficiency: Power user of synthesis and place-and-route tools from Synopsys (DC/FC, ICC2, PrimeTime) and/or Cadence (Genus, Innovus, Tempus).
• Prior experience in data-focused EDA tool evaluation, flow benchmarking, and methodology development with demonstrated PPA impact.
• Strong scripting proficiency in Python, TCL, Perl, and/or Make for flow automation and analysis.
• Demonstrated ability to drive complex, cross-functional technical initiatives — aligning build, CAD, and EDA vendor teams toward shared goals.
• Excellent problem-solving, debugging, and analytical skills with a track record of simplifying complex environments.
• Strong interpersonal and communication skills; able to translate technical findings into actionable recommendations.

Responsibilities

• Own and continuously improve the end-to-end RTL2GDS implementation methodology for advanced-node CPU builds.
• Evaluate new EDA tools and process node capabilities; advise on adoption and vendor roadmaps.
• Define and enforce implementation methodology BKMs and flow standards; maintain documentation and train teams.
• Build and run rigorous A/B and multi-variant experiments to compare flows and QoR impact.
• Drive aggressive PPA targets; diagnose timing, power, and QoR issues and scale solutions.
• Architect and build Python/TCL/Perl automation frameworks to reduce engineering effort.
• Identify bottlenecks in the implementation flow and drive automation and AI/ML-assisted optimization.
• Collaborate with architecture, RTL, DFT, physical build, and sign-off teams to realize silicon impact.

Education

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Synopsys DC/FC/ICC2

PrimeTime

Genus

Innovus

Tempus

Python

TCL

Perl

Make

Job description

NVIDIA is seeking an experienced ASIC Implementation Engineer in Santa Clara to own the RTL2GDS methodology for advanced CPU builds. You will evaluate EDA tools, define standards, and lead automation efforts to boost PPA across the design cycle.

Responsibilities include driving flow optimization, conducting QoR experiments, and collaborating with architecture, RTL, DFT, and physical teams to maximize silicon performance. The role emphasizes scripting, data-driven analysis, and vendor interaction.