RTL Design Engineer

Dormont Manufacturing Co; United States; On-site; USD 120,000 - 225,000; Full time

Job summary

Mythic is hiring experienced RTL Design Engineers from junior to senior levels to design and implement the components powering our next-generation AI processors.

As part of the RTL design team, you will own microarchitecture and RTL implementation, optimize high-performance, low-power datapaths, collaborate with architecture, verification, and physical design teams, and contribute to timing closure and design reviews across the full silicon stack.

Qualifications

• Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
• 3+ years of industry experience in RTL design, microarchitecture, and architecture development.
• Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies).
• Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.
• Familiarity with timing constraints, physical design considerations, and EDA flows.
• Hands‑on experience with simulation, synthesis, linting, and static timing analysis tools.
• Strong problem‑solving and communication skills with ability to work in cross‑functional teams.

Responsibilities

• Design and implement RTL for Mythic’s next-generation AI processor.
• Develop and optimize high-performance, low-power components including datapaths, controllers, memory subsystems, and interconnects.
• Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness.
• Drive timing closure by working with synthesis and physical design teams.
• Participate in design reviews and contribute to improving RTL coding practices and methodologies.

Skills

Verilog/SystemVerilog

Timing constraints

Synthesis & static timing

Cross-functional collaboration

Education

Bachelor’s/Master’s/PhD in EE/CE/CS

Tools

Simulation tools

Synthesis tools

Linting tools

Job description

We’re hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

$120,000–$225,000+ annually (salary range). Actual compensation depends on experience, skills, qualifications, and location.

RTL Design at Mythic

At Mythic, our RTL design team is at the heart of transforming our custom dataflow architecture into working silicon. RTL engineers take ownership of microarchitecture and RTL implementation, designing high-performance, low-power logic that enables our breakthrough AI hardware. The team works closely with architecture, custom analog IP, compiler, verification, emulation, and post-silicon teams to ensure every component integrates seamlessly into the full system. Because modern AI workloads push the limits of performance, memory, and efficiency, our RTL engineers apply creativity and rigor to deliver designs that meet aggressive PPA (performance, power, area) goals while ensuring correctness. We welcome engineers at all levels who are excited to tackle challenging design problems and play a key role in building the next generation of AI compute hardware.

Responsibilities

• Design and implement RTL for Mythic’s next-generation AI processor.
• Develop and optimize high-performance, low-power components including datapaths, controllers, memory subsystems, and interconnects.
• Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness.
• Drive timing closure by working with synthesis and physical design teams.
• Participate in design reviews and contribute to improving RTL coding practices and methodologies.

Requirements

• Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 3+ years of industry experience in RTL design, microarchitecture, and architecture development.
• Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies).
• Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.
• Familiarity with timing constraints, physical design considerations, and EDA flows.
• Hands‑on experience with simulation, synthesis, linting, and static timing analysis tools.
• Strong problem‑solving and communication skills with ability to work in cross‑functional teams.