Senior RTL Design Engineer - CPU Frontend

SiFive; Santa Clara (CA); On-site; USD 158,760 - 194,040; Full time

Job summary

SiFive is seeking a CPU design engineer in the Santa Clara area to architect and implement features for RISC‑V core generators using Chisel. You will integrate design content into Chisel/FIRRTL, verify through testbenches, and collaborate with design and physical teams to meet frequency and power goals.

A strong RTL design and software engineering background with 3+ years of experience is required. The role offers exposure to scalable hardware design and collaboration across multidisciplinary

Qualifications

• BS or MS degree in CS/CE/EE or related field, or equivalent experience.
• 3+ years of design experience.
• CPU RTL design experience in instruction fetch, decode, branch prediction, caches, or TLBs.
• Proficiency in Verilog, SystemVerilog, or VHDL.
• Strong software engineering background: OO, AOP, and functional programming; templated metaprogramming; compiler infrastructures for DSLs; test‑driven development.
• Attention to detail and high‑quality design.
• Team player who values engineering collaboration.

Responsibilities

• Architect, design, and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
• Integrate new design content into Chisel/FIRRTL framework and contribute to improvements for automatic configuration, documentation, verification testbenches, and software packaging.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for performance exploration and optimization.
• Develop microarchitecture specifications.
• Share knowledge through comprehensive documentation and participation in a collaborative design culture.

Skills

3+ years design experience

CPU RTL design

Verilog/SystemVerilog/VHDL

Object-oriented programming

Aspect-oriented programming

Functional programming

Template metaprogramming

Compiler infrastructures for DSLs

Test-driven development

Attention to detail

Team player

Scala/Chisel experience

Bluespec experience

RISC‑V knowledge

Git/Github/Jira/Confluence

Education

BS or MS degree in CS/CE/EE or related field

Tools

Git

Github

Jira

Confluence

Chisel

Job description

Overview

SiFive is a pioneer in RISC‑V technology, delivering high‑performance, data‑intensive computing solutions across artificial intelligence, machine learning, automotive, data center, mobile, and consumer markets.

Responsibilities

• Architect, design, and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements for automatic configuration, documentation, verification testbenches, and software packaging.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for performance exploration and optimization.
• Develop microarchitecture specifications.
• Share knowledge through comprehensive documentation and participation in a collaborative design culture.

Qualifications

• BS or MS degree in computer science, computer engineering, electrical engineering, or related field, or equivalent experience.
• 3+ years of design experience.
• Academic or professional experience with CPU RTL design in instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, or TLBs.
• Proficiency in hardware (RTL) design with Verilog, SystemVerilog, or VHDL.
• Strong software engineering background, including object‑oriented, aspect‑oriented, and functional programming; templated metaprogramming; compiler infrastructures for domain‑specific languages; data modeling for optimizing compiler passes; test‑driven development.
• Attention to detail and a focus on high‑quality design.
• Team‑player who values engineering collaboration.

Nice‑to‑Haves

• Experience with Scala/Chisel, Bluespec, or other language/DSL for expressing configurable hardware via software.
• Knowledge of RISC‑V architecture.
• Expertise in CPU processor designs such as instruction fetch, instruction decode, register renaming and instruction scheduling, vector units, or load‑store units.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git, Github, Jira, Confluence.

Pay & Benefits

Consistent with SiFive values and applicable law, we provide a market‑based pay structure that varies by location. The base pay range for this role is $158,760.00 – $194,040.00. In addition to base pay, the role may be eligible for variable/incentive compensation and/or equity. A comprehensive, competitive benefits package may include healthcare, retirement plans, paid time off, and more.

Additional Information

This position requires successful background and reference checks and proof of eligibility to work in the United States. Employment offers are contingent on confirming authorization to access export‑controlled technology under applicable export control laws or obtaining necessary licenses or approvals.

Equal Employment Opportunity

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire.