Senior Power Integrity Engineer for AI Server Systems

Socket.dev; Los Altos (CA); On-site; USD 180,000 - 270,000; Full time

Job summary

Majestic Labs seeks a Senior Power Engineer to lead board-, server-, and rack-level power delivery architecture for multi-kilowatt AI server platforms. You will own end-to-end PDN design, define voltage conversion strategy, and drive reliable, efficient power paths compatible with OCP/Open Rack standards.

You will collaborate with silicon, mechanical, thermal, and systems engineers to optimize impedance, transient response, and overall system performance across high-current interfaces.

Qualifications

• BS/MS in Electrical Engineering or related field.
• 10+ years of experience in high-power delivery design.
• Demonstrated experience designing high-current, low-voltage power delivery for SoCs.
• Deep expertise in power integrity, PDN modeling, VRM design, target impedance definition, and transient response optimization.
• Proficiency with SPICE, PDN simulation tools (Keysight, Cadence Sigrity/Clarity, Ansys SIwave), and measurement equipment (VNAs, oscilloscopes, electronic loads).
• Solid understanding of package-to-PCB PDN interactions.
• Strong communication and cross-functional collaboration skills.

Responsibilities

• Architect and design board-level, server-level, and rack-level power delivery systems for high-power subsystems.
• Define PDN topology, including VRMs, POLs, vertical and lateral power routing, and high-current interfaces.
• Perform component selection (VRMs, FETs, inductors, bulk caps, MLCCs, connectors, busbars) and create derating, margin, and reliability guidelines.
• Lead decoupling capacitor strategy across package and PCB layers to meet target impedance and transient response goals.
• Drive power integrity analysis (AC/DC, Z-target, transient, EMI/EMC) and validate designs through modeling, simulation, and lab measurement.
• Collaborate with mechanical and thermal teams to ensure high-current routing, cooling requirements, and system constraints are aligned.
• Partner with silicon and package engineering to co-design vertical PDN paths, including socket interfaces, pin/bump maps, and transient load profiles.
• Develop test plans for PDN validation, transient load tests, impedance measurement, and system bring-up.
• Provide expertise during failure analysis, root-cause investigations, and corrective actions for system power issues.

Skills

Power integrity

PDN design

VRM design

Spice

PDN modeling

High-current design

Cross-functional collaboration

Education

BS/MS in Electrical Engineering

Tools

SPICE

Keysight

Cadence Sigrity/Clarity

Ansys SIwave

VNAs

Job description

Majestic Labs seeks a Senior Power Engineer to lead board-, server-, and rack-level power delivery architecture for multi-kilowatt AI server platforms. You will own end-to-end PDN design, define voltage conversion strategy, and drive reliable, efficient power paths compatible with OCP/Open Rack standards.

You will collaborate with silicon, mechanical, thermal, and systems engineers to optimize impedance, transient response, and overall system performance across high-current interfaces.