Senior PLL Design Engineer — Frequency Synthesis IP

Apple Inc.; San Diego (CA); On-site; USD 175,000 - 308,500; Full time

Benefits offered by this job

Stock programs

Medical and dental coverage

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. is seeking an engineering leader in the Analog-Mixed/Signal group to push the boundaries of frequency synthesis in SOC/PHY designs and high-quality hard IPs. You will collaborate across teams to meet tight production schedules and contribute to market-leading innovation.

In this role you will design PLL/FLL architectures, DCO/VCO, and implement jitter reduction, SystemVerilog models, and RTL debugging. You will grow within a fast-paced, learning-driven environment at Apple.

Qualifications

• Bachelor of Science in Electrical Engineering (BSEE) with at least 10 years of relevant experience.
• Demonstrated proficiency in PLL/FLL and frequency synthesis architecture (DCO/VCO, Fractional-N, SSC, Spur/Jitter cancellation).
• Knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques.
• Strong clocking fundamentals: phase noise, jitter budgeting, and feedback loop dynamics.
• Experience in SystemVerilog modeling and behavioral simulations; RTL design is a plus.
• Attention to detail with a track record of innovation and learning; strong teamwork and scripting skills.

Job description

Apple Inc. is seeking an engineering leader in the Analog-Mixed/Signal group to push the boundaries of frequency synthesis in SOC/PHY designs and high-quality hard IPs. You will collaborate across teams to meet tight production schedules and contribute to market-leading innovation.

In this role you will design PLL/FLL architectures, DCO/VCO, and implement jitter reduction, SystemVerilog models, and RTL debugging. You will grow within a fast-paced, learning-driven environment at Apple.