Senior PIC Test Architect - Wafer & Die Level

Xscape Photonics Inc; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Restaurant of test lab

Competitive compensation

Job summary

Xscape Photonics Inc. in Santa Clara, CA, seeks an experienced PIC Test Engineer to own wafer-level and die-level test strategy across the full product lifecycle from silicon bring-up to high-volume manufacturing.

You will lead test architecture, DFT collaboration, and scalable wafer probing solutions to drive robust, repeatable test content. The ideal candidate has 10+ years in PIC test engineering, proven ownership of test strategies, and a track record of scale-up across multiple nodes and

Qualifications

• 10+ years of experience in PIC test engineering, wafer-level probing, or photonics manufacturing test.
• Proven ownership of wafer-level optical/electrical test strategy from R&D through HVM.
• Experience with PIC DFT and collaborating with PDK development teams.

Responsibilities

• Define and own the wafer-level PIC test roadmap across multiple product lines and technology platforms.
• Architect scalable, high-throughput optical + electrical wafer probe solutions, balancing alignment accuracy, probe stability, and test time.
• Establish release criteria, guard-banding strategy, and wafer test coverage models aligned with product requirements.
• Define and own tests not carried out at wafer level (e.g., Optical Vector Analysis, polarization-resolved testing).
• Lead first-silicon bring-up efforts, including test content definition, limit setting, and characterization flows.
• Drive rapid yield-learning loops in partnership with design, process integration, and fabrication teams.
• Enable fast debug and iteration during early node transitions and new platform ramps.
• Influence PIC Design-for-Test features and PDK structures to improve wafer-level scalability (on-chip monitors, loopback paths, test waveguides, calibration structures).
• Embed manufacturable test hooks early in the development cycle.
• Own wafer-level yield, parametric distributions, and systematic defect learning.

Skills

Wafer-level optical probing

Die-level test development

Test time optimization

Yield learning and spatial analysis

Job description

Xscape Photonics Inc. in Santa Clara, CA, seeks an experienced PIC Test Engineer to own wafer-level and die-level test strategy across the full product lifecycle from silicon bring-up to high-volume manufacturing.

You will lead test architecture, DFT collaboration, and scalable wafer probing solutions to drive robust, repeatable test content. The ideal candidate has 10+ years in PIC test engineering, proven ownership of test strategies, and a track record of scale-up across multiple nodes and