Senior Physical Verification Engineer — Advanced CMOS

Intel Corporation; United States; Hybrid; USD 129,000 - 245,000; Full time

Benefits offered by this job

Hybrid work model

Competitive compensation

Stock bonuses

Job summary

Intel Foundry Services seeks an Aerospace, Defense & Government Senior Physical Verification Application Engineer to support layout verification and parasitic extraction, helping tape-outs across advanced CMOS processes.

You will lead verification workflows, develop best practices, create documentation and trainings, and collaborate with customers, IP providers, and EDA vendors, leveraging 22nm and below processes in a hybrid US-based role.

Qualifications

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelor’s degree in Electrical / Computer Engineering, Computer Science, or STEM.
• 3+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years of experience in layout verification and parasitic extraction EDA tools.
• 3+ years of scripting (Python, Perl, Tcl, or shell).

Responsibilities

• Provide technical support on layout verification and parasitic extraction challenges.
• Collaborate with internal teams, customers, IP providers and EDA vendors on rules and extraction issues.
• Lead optimization of physical verification flows for advanced CMOS processes (22nm and below).
• Create application notes, training materials and best practice guidelines.
• Deliver customer-facing technical support and assist with complex verification issues.

Skills

US Citizenship

Security clearance eligibility

Scripting (Python, Perl, Tcl, shell)

Analytical problem solving

Education

Bachelor’s degree in Electrical/Computer Engineering or STEM

Tools

ICV

Calibre

Pegasus EDA tools

StarRC/Quantus/xACT

Job description

Intel Foundry Services seeks an Aerospace, Defense & Government Senior Physical Verification Application Engineer to support layout verification and parasitic extraction, helping tape-outs across advanced CMOS processes.

You will lead verification workflows, develop best practices, create documentation and trainings, and collaborate with customers, IP providers, and EDA vendors, leveraging 22nm and below processes in a hybrid US-based role.