Physical Verification Engineer

Intel; Hillsboro (OR); On-site; USD 128,880 - 245,160; Full time

Benefits offered by this job

Competitive compensation

Health benefits

Retirement plans

Vacation

Job summary

Intel is seeking a Senior Physical Verification Application Engineer in Hillsboro, Oregon, to support their Foundry Services customers. The role involves addressing complex design verification challenges, driving quality improvements, and providing technical guidance on advanced methodologies.

The ideal candidate will possess a Bachelor's in a STEM field, with a minimum of 3 years experience in layout verification and EDA tools, with strong analytical and communication skills.

Qualifications

• US Citizenship required.
• Bachelor's degree in a relevant STEM field.
• 3+ years of experience with advanced CMOS processes.
• 3+ years in layout verification and parasitic extraction.

Responsibilities

• Provide technical support on layout verification for customers.
• Create application notes and documentation for verification workflows.
• Lead optimization of physical verification flows for advanced CMOS processes.
• Deliver customer-facing technical support and solutions.

Skills

Layout verification

Parasitic extraction

Technical communication

Problem-solving

Scripting languages (Python, Perl, Tcl)

Education

Bachelor's degree in Electrical / Computer Engineering, Computer Science, or STEM-related field

Tools

StarRC

Quantus

Calibre

Pegasus

Job description

About Intel Foundry Services

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting‑edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry‑leading technology, a rich IP portfolio, a world‑class design ecosystem, and an operationally resilient global manufacturing supply chain.

Position Overview

The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape‑outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.

Key Responsibilities

• Physical Verification Support & Issue Resolution: Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges; collaborate with internal Intel teams and external stakeholders; resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations.
• Technical Content Development & Training: Create application notes, comprehensive documentation, deliver technical training presentations to customers and internal teams; drive quality improvements in design kits and documentation; develop best practice guidelines for physical verification flows and methodologies across advanced process technologies.
• Verification Methodology Leadership: Lead optimization of physical verification flows for advanced CMOS processes (22nm and below); provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations; drive methodology improvements to streamline customer design workflows and enhance verification productivity.
• Customer Engagement & Technical Excellence: Deliver customer‑facing technical support with focus on physical verification challenges and solutions; support customers through complex verification issues and advanced process technology adoption; ensure maximum customer satisfaction through expert guidance and responsive technical support.

Core Competencies

• Self‑driven and results‑oriented with capability to effectively manage multiple complex tasks.
• Strong analytical problem‑solving skills for complex physical verification challenges.
• Effective communication skills with experience in collaboration, active listening, and providing constructive feedback.

Minimum Qualifications

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• 3+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years of combined experience in layout verification and parasitic extraction EDA tools.
• 3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting).

Preferred Qualifications

• Active US Government Security Clearance with a minimum of Secret level.
• Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Hands‑on experience in one or more areas (LVS, DRC, ERC, PERC).
• Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA tools.
• Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools.
• Rule deck coding experience in ICV, Calibre or Pegasus EDA tools.
• Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work.
• Customer facing experience.

What We Offer

• Opportunity to work with cutting‑edge physical verification technologies for aerospace, defense, and government applications.
• Direct customer engagement and technical leadership in advanced semiconductor verification.
• Access to Intel's most advanced foundry technologies and comprehensive verification tool suites.
• Competitive compensation.
• Professional development in physical verification methodologies and foundry services.
• Direct impact on national security through advanced semiconductor verification solutions.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
• Annual Salary Range for jobs which could be performed in the US: $128,880.00 - 245,160.00 USD.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.