Senior Physical Design Integration Engineer

Dormont Manufacturing Co; Folsom (CA); On-site; USD 256,050 - 361,480; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health benefits

Retirement plans

Vacation

Job summary

Dormont Manufacturing Co is looking for a Physical Design Integration Engineer in Folsom, California. This role involves leading the physical design implementation of custom CPU designs, optimizing CPU performance and collaborating closely with various teams.

The ideal candidate will have a Bachelor’s degree in Electrical/Computer Engineering and significant experience in logic and VLSI/ASIC design. This position offers a competitive salary and a hybrid work model, emphasizing collaboration across teams.

Qualifications

• 15+ years relevant work experience with a Bachelor's, or 12+ with a Master's.
• Proven experience in full ASIC design flow.
• Strong leadership and communication skills.

Responsibilities

• Lead physical design and optimization flows.
• Define design requirements for new technologies.
• Collaborate with project teams to resolve design issues.

Skills

Logic design

VLSI/ASIC design

Computer architecture

Leadership

Communication

Unix/Linux

Perl

TCL

Education

Bachelor’s in Electrical/Computer Engineering

Master’s in Electrical/Computer Engineering

Job description

Job Details:

At the Data Center Group (DCG), we’re committed to delivering exceptional products and delighting our customers.

The Physical Design Integration Engineer performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.

Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.

Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a high‑speed, low‑power synthesizable CPU. Optimizes CPU design to improve product‑level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Responsibilities

• Lead all SoC level physical design and optimization flows ranging from floor‑planning, clocking, synthesis through GDS and parallel verification aspects such as static timing analysis, formal verification, EM/IR/PDN verification, quality assurance, layout verification, etc.
• Define design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures.
• Work closely with the project team to resolve issues that arise during the design cycle and incorporate learnings into subsequent product cycles.
• Collaborate with architecture and design teams to improve IP and ultimate product quality and performance.
• Maintain and enhance tool capabilities in collaboration with industry EDA vendors.

Qualifications

• Bachelor’s in Electrical/Computer Engineering with 15+ years relevant work experience, or Master’s in Electrical/Computer Engineering with 12+ years relevant work experience.
• Proven experience in logic design, VLSI/ASIC design, and computer architecture.
• Experience in a full ASIC design flow: floorplanning, clock construction, synthesis, place and route, static timing analysis, layout verification.
• Experience with Unix/Linux, Perl, and TCL for creating flexible automation scripts.
• Strong leadership and communication skills; capable of leading a small team and interacting with architecture and design teams.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, California, Folsom

Additional Locations

US, California, Santa Clara

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended background investigation, which includes (subject to country law) extended education, SEC sanctions, and additional criminal and civil checks.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range for jobs which could be performed in the US: $256,050.00-361,480.00 USD. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training.

Work Model for this Role

This role will be eligible for our hybrid work model, allowing employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.