Senior Physical Design Engineer, Neuromorphic AI Hardware

Intel Corporation; Folsom (CA); Hybrid; USD 164,000 - 269,000; Full time

Job summary

Intel Corporation seeks a senior physical design engineer to drive advanced semiconductor integration, including chiplet and packaging technologies, within its neuromorphic silicon team. You will lead floorplan design, timing and power constraints, and collaborate with RTL to reach performance and area targets.

You will use scripting to optimize flows, apply asynchronous design concepts, and push innovation in AI-enabled automation for high-performance AI workloads.

Qualifications

• Bachelor's degree or higher in Electrical Engineering with 4+ years of hands-on physical design experience or a Master’s with 4+ years delivering silicon tape-outs.
• 6+ years of setting up floorplans, timing and power constraints and iterating through synthesis, place-and-route to meet KPIs.
• 6+ years of scripting with Perl, TCL, Python, etc.
• 4+ years debugging FEV/RV reports and planning ECOs.
• 2+ years chiplet integration and/or advanced packaging.
• 1+ year AI tool usage for tool-flow setup, debugging and productivity.

Responsibilities

• Understand system specs to drive package and die-level requirements.
• Architect full-chip floorplans and partition-level floorplans with macro/pin placements and keep-outs.
• Define timing constraints with RTL designers; run synthesis and place-and-route trials; fix timing, EM/IR, LVS and DRC violations.
• Run back-annotated VCS+SDF simulations and iterate to meet power/performance targets.
• Write custom scripts and define tool flows to optimize synthesis and physical design for low power/high performance designs.

Skills

Physical design

Floorplanning

Scripting

Debugging FEV/RV

Chiplet integration

Advanced packaging

AI tool usage

Education

Bachelor's degree or higher in Electrical Engineering

Tools

Cadence Virtuoso

Fusion Compiler

PrimeTime

StarRC

VCS

Job description

Intel Corporation seeks a senior physical design engineer to drive advanced semiconductor integration, including chiplet and packaging technologies, within its neuromorphic silicon team. You will lead floorplan design, timing and power constraints, and collaborate with RTL to reach performance and area targets.

You will use scripting to optimize flows, apply asynchronous design concepts, and push innovation in AI-enabled automation for high-performance AI workloads.