Senior Performance Compiler Engineer (Triton/MLIR) for AI GPU

NVIDIA Corporation; Redmond (WA); On-site; USD 184,000 - 288,000; Full time

Job summary

NVIDIA Corporation is seeking a Senior Performance Compiler Engineer to join the open-source Triton compiler project and optimize AI workloads on NVIDIA GPUs.

You will design and implement compiler techniques with MLIR, explore GPU hardware architectures, and experiment with advanced numerics to unlock higher performance. When needed, inline PTX to hand-tune critical paths and collaborate with CUDA teams to ensure sustained efficiency across training and inference workloads.

Qualifications

• Bachelor, Masters or Ph.D. degree or equivalent experience in Computer Science, Computer Engineering, Applied Math, or a related field.
• 8+ years of relevant industry experience in software development.
• Strong C++ programming and software design skills with performance analysis and debugging.
• Experience in parallel programming, including CUDA/OpenCL GPU programming or other parallel models such as OpenMP.
• Solid understanding of computer architecture and hands-on assembly-level programming.

Responsibilities

• Investigating the latest and future NVIDIA GPU hardware architecture and programming models.
• Designing and implementing compiler technology using MLIR to optimize high-level kernel descriptions, with focus on efficient GPU code.
• Hand-tuning critical code paths with inline PTX to extract peak performance.
• Collaborating with hardware architects and CUDA compiler team to influence future products.

Skills

C++ programming

Performance analysis

Debugging

Parallel programming

Education

Bachelor's degree or higher (CS/CE/Applied Math)

Advanced degree in related field

Tools

CUDA

OpenCL

MLIR

Job description

NVIDIA Corporation is seeking a Senior Performance Compiler Engineer to join the open-source Triton compiler project and optimize AI workloads on NVIDIA GPUs.

You will design and implement compiler techniques with MLIR, explore GPU hardware architectures, and experiment with advanced numerics to unlock higher performance. When needed, inline PTX to hand-tune critical paths and collaborate with CUDA teams to ensure sustained efficiency across training and inference workloads.