Senior PDK Physical Verification Engineer

Intel Corporation; Santa Clara (CA); Hybrid; USD 150,000 - 285,000; Full time

Job summary

Intel Corporation’s Design Technology Platform (DTP) organization seeks a skilled engineer to advance density fill methodologies and PDK solutions for the most advanced process technologies. You will work at the intersection of process technology, physical verification, and design automation, shaping manufacturability improvements and enabling high-performance IC designs.

You will collaborate with cross-functional teams, develop robust validation frameworks, and drive automation to scale

Qualifications

• Bachelor's degree or higher in a technical field with 6+ years of experience; or Master's with 5+ years; or PhD with 2+ years.
• 4+ years with Calibre/ICV/Pegasus including development, debugging, validation, or deployment.
• 3+ years with SVRF/TVF/PXL/PVL/Tcl environments.
• Experience with process technology, device physics, design rules, and manufacturability.
• Algorithmic solutions for physical design and manufacturing challenges at advanced nodes.
• Unix/Linux computing environments.

Responsibilities

• Lead development and validation of density fill solutions within advanced PDks.
• Develop algorithms using Calibre, ICV, and Pegasus to ensure density compliance.
• Collaborate with process integration, design rule owners, and customers to define requirements.
• Drive automation to improve efficiency and deployment across environments.
• Create validation frameworks, test suites, and qualification methodologies for tool releases.
• Advance physical verification methodologies for scaling technologies.
• Partner with external EDA vendors to deploy next-generation tool capabilities.
• Prepare technical docs and training materials for Intel's design community.
• Serve as a technical expert contributing to Intel's design enablement roadmap.

Skills

Density fill

Algorithm development

Physical verification

Unix/Linux

Rule deck debugging

SVRF/TVF/PXL

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Master's degree

PhD

Tools

Calibre

ICV

Pegasus

Cadence Virtuoso

Synopsys Custom Designer

Job description

Job Details:

Job Description:

Shape the Future of Advanced Semiconductor Technology at Intel

Join Intel's Design Technology Platform (DTP) organization and become part of a world-class team enabling the next generation of semiconductor innovation. In this highly visible role, you will develop and deploy advanced density fill methodologies and Process Design Kit (PDK) solutions that directly impact Intel's most advanced technology nodes and product designs.

Working at the intersection of process technology, physical verification, and design automation, you will collaborate with leading engineers across Intel and the EDA ecosystem to solve complex manufacturability challenges, improve design productivity, and enable breakthrough technologies. Your contributions will influence how future products are designed and manufactured, helping Intel maintain technology leadership in an increasingly competitive industry.

What You’ll Do

• Lead the development, implementation, and validation of density fill solutions within advanced Process Design Kits (PDKs).
• Develop algorithmic solutions using industry-leading physical verification platforms, including Calibre, Synopsys ICV, and Cadence Pegasus, to ensure density compliance and manufacturability across advanced process technologies.
• Collaborate with process integration teams, design rule owners, product design engineers, and customers to define requirements and deliver state-of-the-art solutions.
• Drive automation initiatives that improve engineering efficiency, solution scalability, and deployment across multiple design environments.
• Design and develop robust validation frameworks, test suites, and qualification methodologies to ensure high-quality tool and rule deck releases.
• Advance innovative physical verification methodologies to address emerging challenges associated with technology scaling.
• Partner closely with external EDA vendors to influence and deploy next-generation tool capabilities and methodologies.
• Develop technical documentation, training materials, and best practices that enable successful adoption across Intel's design community.
• Serve as a technical expert and contribute to strategic initiatives that shape Intel's design enablement roadmap.

Ideal Candidate Background

We are particularly interested in candidates who have developed physical verification methodologies, density-fill solutions, or PDK technologies within:

• Semiconductor Foundries.
• Integrated Device Manufacturers (IDMs).
• Advanced Packaging and OSAT Organizations.
• EDA Software Companies.
• Design Enablement or CAD Teams supporting advanced-node development.

Core Competencies

• Excellent communication and technical presentation skills, with the ability to translate complex technical concepts into actionable solutions.
• Strong problem‐solving, debugging, and analytical skills.
• Strong understanding of technology scaling challenges and their impact on physical verification and design rule development.

Qualifications

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 6+ years of relevant experience; OR - Master's degree with 5+ years of experience.
• OR - PhD with 2+ years of experience.
• 4+ years of hands-on experience with at least one industry-standard physical verification platform such as Calibre, ICV, or Pegasus, including methodology development, rule deck debugging, validation, or production deployment.
• 3+ years of experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, PVL, or Tcl‑based verification environments.
• Experience with semiconductor process technology, device physics, design rules, and manufacturability requirements.
• Experience developing algorithmic solutions for physical design and manufacturing challenges at advanced technology nodes.
• Experience with with Unix/Linux operating systems and engineering computing environments.

Preferred Qualifications

• 4+ years of direct experience developing, deploying, or supporting density fill methodologies for advanced semiconductor technologies at 16nm and below.
• Proven expertise in fill rule implementation, density optimization, and manufacturing-driven design methodologies.
• Deep experience with physical verification flows, including DRC, density analysis, fill verification, and process-aware design enablement.
• Experience supporting or developing solutions for leading foundry, IDM, or advanced process technologies.
• Familiarity with custom layout environments such as Cadence Virtuoso or Synopsys Custom Designer.
• Experience collaborating across multidisciplinary engineering teams and external partners to deliver innovative solutions.
• Experience leading technical initiatives, driving process improvements, or influencing product and methodology roadmaps.
• Prior experience with semiconductor foundries, IDMs, OSATs, or EDA vendors developing physical verification methodologies, density-fill solutions, PDKs, or design-for-manufacturing technologies is highly desirable.

Why Intel?

This role offers a rare opportunity to work on technology challenges that influence the future of semiconductor manufacturing. You'll collaborate with experts across process technology, CAD, physical design, and EDA while helping define methodologies used across Intel's most advanced products. If you are passionate about solving complex physical verification and manufacturability problems at scale, this role offers both significant technical depth and broad organizational impact. Join Intel and make a direct impact on the next generation of semiconductor innovation.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust: N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.