Senior PCB Layout Engineer – High-Speed Networking

TP-Link Systems USA; Irvine (CA); On-site; USD 165,000 - 175,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401k plan

Paid time off

Bi-annual raises

Gym membership

Job summary

TP-Link Systems USA is seeking a Senior PCB Layout Engineer to join our engineering team in Irvine, CA. You will manage complex PCB designs with thousands of components, collaborate with hardware and mechanical engineers, and drive layouts from concept to mass production.

Requirements include 5+ years in PCB layout, a B.S. in Electrical Engineering, and proficiency with OrCAD or Allegro. You will help create reliable footprints and libraries and mentor junior engineers.

Qualifications

• 5+ years of PCB layout experience.
• Bachelor’s degree in Electrical Engineering.
• Ability to read and interpret schematics and apply best practices for each design.
• Experience using EDA tools to drive board-level PCB design.

Responsibilities

• Work with hardware and mechanical-structural teams to drive PCB design and layout.
• Output reliable design files and support fabrication issues and EQ responses.
• Assess feasibility, schedule risks, cost targets, and manufacturability of layouts.
• Own creation and maintenance of PCB footprints and libraries.
• Mentor junior PCB Layout engineers and contribute to CAD team training and standards.

Skills

PCB layout design

Schematic reading

Team collaboration

Communication skills

Hardware collaboration

Education

Bachelor's degree in Electrical Engineering

Tools

OrCAD

Allegro

Job description

TP-Link Systems USA is seeking a Senior PCB Layout Engineer to join our engineering team in Irvine, CA. You will manage complex PCB designs with thousands of components, collaborate with hardware and mechanical engineers, and drive layouts from concept to mass production.

Requirements include 5+ years in PCB layout, a B.S. in Electrical Engineering, and proficiency with OrCAD or Allegro. You will help create reliable footprints and libraries and mentor junior engineers.