Senior PCB Design Engineer - High-Speed Multilayer Layout

Motive Workforce Solutions; Los Angeles (CA); On-site; USD 83,000 - 124,000; Full time

Job summary

Motive Workforce is seeking a Senior PCB Layout and Design Engineer for the greater Los Angeles area, onsite in Canoga Park, CA. This contract opportunity requires US citizenship and offers potential for direct hire.

The role focuses on leading the physical design and layout of complex PCBs, translating schematics into manufacturable designs, and collaborating with cross-functional teams. Responsibilities include defining stackups, routing, signal integrity, power integrity, and manufacturing

Qualifications

• Senior PCB Layout and Design Engineer with leadership experience.
• Ability to translate schematics into manufacturable PCB layouts.
• Experience with high-speed digital, analog, mixed-signal, RF, and power circuitry.

Responsibilities

• Develop layouts for multilayer PCBs with high-speed digital, analog, mixed-signal, RF, and power circuitry.
• Define board stackups, component placement, routing constraints, and fabrication requirements with engineering teams and PCB suppliers.
• Apply signal integrity, power integrity, impedance control, grounding, shielding, and thermal-management principles.
• Route critical interfaces, including differential pairs, clocks, memory buses, and timing-sensitive signals.
• Coordinate electrical and mechanical requirements, including outlines, connector locations, mounting features, and enclosure clearances.
• Perform design-rule checks and resolve layout, connectivity, clearance, and manufacturing issues.

Job description

Motive Workforce is seeking a Senior PCB Layout and Design Engineer for the greater Los Angeles area, onsite in Canoga Park, CA. This contract opportunity requires US citizenship and offers potential for direct hire.

The role focuses on leading the physical design and layout of complex PCBs, translating schematics into manufacturable designs, and collaborating with cross-functional teams. Responsibilities include defining stackups, routing, signal integrity, power integrity, and manufacturing