Senior PCB Layout & High-Speed Design Engineer

Butler America Aerospace L.L.C.; Los Angeles (CA); On-site; USD 91,000 - 103,000; Full time

Benefits offered by this job

401K

Medical Insurance

Dental

Vision

Sick Time

Job summary

Butler America Aerospace, LLC. is seeking a Senior PCB Layout and Design Engineer to lead complex multilayer PCB design from concept to production at Canoga Park, CA.

The role focuses on high-speed, RF and power circuitry with cross-functional collaboration across electrical, mechanical, manufacturing, and test teams. You will define stackups, routing constraints, run DFM/DFT checks, and generate fabrication outputs while mentoring junior designers and driving design standards.

Qualifications

• Bachelors in Electrical Engineering or related field.
• Typically 7+ years of PCB layout and design experience.
• Experience with multilayer boards and high-speed routing.

Responsibilities

• Develop layouts for multilayer PCBs with high-speed circuits.
• Define stackups, placement, routing constraints and fabrication needs.
• Apply signal and power integrity, impedance control and thermal management.
• Route critical interfaces and coordinate with mechanical and PCB suppliers.
• Produce fabrication/assembly drawings, drill files, and Gerber data.
• Lead design reviews and mentor junior designers.

Skills

Altium Designer

PCB Layout & Routing

High-Speed / HDI Layout

Signal Integrity / Power Integrity

IPC Standards knowledge

Schematic Interpretation

DFM/DFT

Cross-Functional Collaboration

Documentation & Release Management

Education

Bachelor's degree in Electrical Engineering

Tools

OrCAD Designer

Mentor Graphics Board Station

Windchill PLM

Job description

Butler America Aerospace, LLC. is seeking a Senior PCB Layout and Design Engineer to lead complex multilayer PCB design from concept to production at Canoga Park, CA.

The role focuses on high-speed, RF and power circuitry with cross-functional collaboration across electrical, mechanical, manufacturing, and test teams. You will define stackups, routing constraints, run DFM/DFT checks, and generate fabrication outputs while mentoring junior designers and driving design standards.