Senior Micro-Architect - I/O Memory Management

Intel Corporation; Santa Clara (CA); On-site; USD 161,000 - 228,000; Full time

Job summary

An established industry player is seeking a skilled engineer to join their innovative team. This role involves developing cutting-edge technology that enhances product performance and competitiveness. As a key contributor, you'll work on logic design, RTL coding, and ensure high-quality integration and verification of IP blocks. Collaborate with talented professionals in a dynamic environment that values creativity and technical excellence. If you're passionate about engineering and eager to make a difference, this opportunity is perfect for you!

Benefits

Competitive pay

Stock options

Bonuses

Health benefits

Retirement plans

Vacation time

Qualifications

• 4+ years of experience in microarchitecture design and MAS development.
• Proficient in RTL coding and debugging pre-silicon validation failures.

Responsibilities

• Develop logic design and RTL coding for IP generation.
• Engage in technical discussions to resolve design implementation issues.

Skills

RTL coding

uArch design

debugging and root cause analysis

knowledge in static tool failures

timing report analysis

silicon debug experience

Education

BSEE/MSEE or equivalent

Job description

Job Details:

Job Description:

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

The DCAI and Silicon Eng Team (DASE) deliver leadership Xeon products to cloud and datacenter customers through development of industry leading x86 core and differentiated IPs that enhances product performance and competitiveness in both Xeon and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building blocks for the Xeon server SOCs.

Who You Are

Your responsibilities are as follows but not limited to:

1. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
2. Participates in the definition of architecture and microarchitecture features of the block being designed.
3. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
4. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
5. Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.
6. Is a strong communicator that engages in technical forums/discussions to resolve issues that arise during design implementation.
7. Keeps silicon debug hooks in mind when coding a design.

Qualifications:

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

1. BSEE/MSEE or equivalent with 4+ Years of uArch design and MAS Development to HAS.
2. Proficient in RTL coding.
3. Must be able to debug and root cause pre-silicon volume validation failures quickly.
4. Knowledge in static tool failures and how to fix them in RTL.

Preferred Qualifications

1. Knowledge in timing reports and how to resolve timing failures in RTL.
2. Silicon debug experience.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, Austin

Business group:

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.