Senior MEMS/ROIC Systems Engineer

Itera, Inc.; San Francisco (CA); On-site; USD 150,000 - 200,000; Full time

Benefits offered by this job

Health insurance

401k retirement plan

Equity compensation

Flexible vacation

Job summary

Itera, Inc. seeks a Senior MEMS/ROIC Systems Engineer to bridge the gap between physical topology and our custom silicon. You will own the device-to-ASIC integration, drive and debug ROICs, and build test architectures to characterize electromechanical interactions at the system level.

You will also help scale lab processes toward production. You will work hands-on with glass, silicon, and PCBA, collaborating with materials, electronics, and manufacturing teams to move from lab-scale to

Qualifications

• BS or MS in Electrical Engineering, Applied Physics, or related discipline.
• Strong hands-on experience in a lab environment characterizing analog/ASIC/MEMS devices.
• Deep understanding of ROIC architectures (transimpedance amplifiers, capacitance voltage amplifiers, ADCs).
• Experience writing scripts to control hardware, parse communication protocols (I2C, SPI, I3C).
• Familiarity with precision analog measurement techniques, guarding, shielding, and low-noise signal extraction.
• Comfort working in a startup or fast-paced R&D environment.

Responsibilities

• ROIC Driving & Control: Develop hardware and firmware setups to drive, control, and communicate with ROICs and mixed-signal ASICs.
• Device Debugging & Characterization: Lead lab testing to characterize device performance and identify bottlenecks.
• System Integration: Assemble and test Glass/ASIC multichip modules or PCB prototypes.
• Closed-Loop Control: Implement and optimize PLLs/AGCs to drive variable capacitance loads.
• Cross-Functional Feedback: Provide empirical ROIC feedback to IC design teams and troubleshoot issues.
• Test Automation: Write Python scripts to automate data acquisition and control lab equipment.

Skills

ROIC architectures

Lab characterization

Test automation

Device debugging

Scripting

Education

BS or MS in Electrical Engineering

Tools

Klayout

Python

Job description

Our mission is to break the slow, iterative loop of hardware development by enabling engineers to test and refine electronics at the speed of thought. We are developing a radically new physical architecture that integrates topological computing with active matrix display and MEMS technology as a Field Programmable Metal Array. Our reconfigurable circuit transforms months of waiting into moments of discovery, accelerating the pace of electronic innovation. Our days are spent solving tough manufacturing, physics, and design challenges at the nano to macro scale. We envision a world where anyone can build unprecedented electronics by making hardware that can change almost as easily as software.

What We Value

Passion for your Craft: Show us your personal projects, your passions, your reason for being an engineer. We look for a maker’s attitude and willingness to take on any challenge.

Learner’s Mindset: We focus on learning and thrive in an environment with hard problems and frequent feedback.

High Standards & Continuous Self Improvement: We have high expectations colored by optimism. We prioritize learning, experiment often, and admit when we’re wrong.

We are pushing the boundaries of what is possible and we value people who are hungry to figure out the unknown. We are intellectually honest with a healthy disregard for the impossible.

Role Overview

As a Senior MEMS/ROIC Systems Engineer, your primary mission is to bridge the gap between the physical topology and our custom silicon. You will be responsible for the physical integration, driving, and debugging of the Device-to-ASIC system. You will develop the test architectures to control the ROICs, characterize device physical performance, and debug complex electromechanical interactions at the system level. You will be driving, controlling, and testing the world’s largest 3D-IC that exists between MEMS and picofluidics.

This is a hands‑on role responsible for testing, automation, and debugging on glass, silicon, and PCBA. You’ll work closely with materials, electronics, and manufacturing teams to bring our lab‑scale process into a repeatable, scalable production environment.

Key Responsibilities

ROIC Driving & Control: Develop hardware and firmware setups (using FPGAs, microcontrollers, or precision lab equipment) to drive, control, and communicate with custom ROICs and mixed‑signal ASICs.

Device Debugging & Characterization: Lead hands‑on lab testing to characterize device performance (e.g., resonant frequencies, parasitic capacitance, noise coupling) and identify failure modes or performance bottlenecks.

System Integration: Assemble and test Glass/ASIC multichip modules or PCB‑level prototypes. Work through the complexities of assembly, signal integrity, and grounding.

Closed‑Loop Control: Implement and optimize closed‑loop control algorithms (e.g., phase‑locked loops, AGCs) to drive variable capacitance loads.

Cross‑Functional Feedback: Work directly with the Mixed‑Signal IC design team to provide empirical feedback on ROIC performance. Identify issues like charge injection, offset drift, or noise coupling.

Test Automation: Write Python scripts to automate data acquisition and control of lab equipment (oscilloscopes, spectrum analyzers, source measure units).

Requirements & Attributes

BS or MS in Electrical Engineering, Applied Physics, or a related discipline.

Strong hands‑on experience in a lab environment characterizing analog/ASIC/MEMS devices

Deep understanding of ROIC architectures (transimpedance amplifiers, capacitance voltage amplifiers, ADCs) and how to interface with them.

Experience writing scripts to control hardware, parse communication protocols (I2C, SPI, I3C), and automate testing.

Familiarity with precision analog measurement techniques, including guarding, shielding, and low‑noise signal extraction

Comfort working in a startup or fast‑paced R&D environment.

Bonus Points that Make You Stand Out

Understanding of display device physics and driving including the ability to interpret TFT SPICE models and understand how panel‑level parasitics interact with drivers.

Experience with FPGA design for custom sensor readout and high‑speed data acquisition.

Knowledge of packaging effects on MEMS and ICs, including stress‑induced offsets and parasitic capacitance modeling.

Experience working alongside IC design teams during bring‑up and silicon validation phases.

Experience with sub‑threshold analog circuits, sensor interfaces, or analog compute‑in‑memory.

Prior experience and comfort with open source tools like Klayout

If you don’t meet the exact requirements but have other reasons why you think you would be a good fit, we encourage you to apply and tell us about them. All applications will be reviewed and receive a response from a human.

Compensation: $150,000- $200,000 Salary + Equity

A generous equity plan on top of market‑based competitive salary

No red tape so decisions get made quickly and we stay innovative

Flexible vacation policy to recover and recharge

An in‑person culture where we work hands‑on with the hardware

Employer‑sponsored health insurance with subsidy for family members

401k retirement savings plan

Room for growth in capabilities and scope

At Itera, we don’t just accept differences, we celebrate and support them for the benefit of our employees, our products, and our community. By uniting different perspectives, we imagine new possibilities, inspire innovation, and realize the full potential of our people. Itera is an equal opportunity employer. Employment at Itera is based solely on a person's merit and qualifications directly related to professional competence.