Senior Member of Technical Staff (#90541)

Rival; Santa Clara (CA); On-site; USD 194,000 - 203,000; Full time

Job summary

A leading company in Santa Clara is seeking a skilled verification engineer to work on PCIe protocol designs. The role involves developing verification environments, collaborating with design teams, and ensuring functional correctness. Ideal candidates will have a Master’s in Electrical Engineering and experience with UVM and Cadence tools.

Qualifications

• 2 years of experience in PCIe verification or related occupation.
• Experience in creating verification plans and developing UVC components.

Responsibilities

• Develop and verify PCIe IP/subsystem at IP and subsystem level.
• Collaborate with design teams to debug and verify fixes.

Skills

Verification Environment

Collaboration

Debugging

Education

Master’s in Electrical Engineering

Tools

Cadence eplanner

UVM

Verilog-OVM

Perl

Python

Tcl/Tk

Job description

Utilizing PCIe protocol mainly on PHY and protocol layer, including working on designs that

support PCIe. Work on verification environments like UVM, System Verilog (SV) and C. Work

closely with architects, micro-architects to develop a test plan to be executed for verifying

the PCIE at IP and subsystem level. Responsible for bringing up PCIe verification environments

and building test benches in UVM, SV and C. Responsible for developing tests - both directed

and random to exercise the PCIe IP/subsystem. Help integrate any third-party IPs into the

verification environment. Develop UVM/SV/C based checks for functional correctness, including

transaction order, transaction payload construction and transaction responses. Run regressions,

debug any failures, collaborate with the design/IP teams to get the issues fixed and verify the

fixes in a timely manner. Generate coverage for the design, analyze and close any gaps.

Collaborate with SoC team in leveraging the PCIe IP verification collateral at SoC. Work closely

with Firmware and Software teams to test the firmware images/ software to be run

with PCIe design. Support all verification activities and the SoC through successful tape out.

Assist in post-silicon debug activities once the chip comes back and guide junior engineers in the

team on PCIe verification activities.

Education:

• Master’s or foreign equivalent in Electrical Engineering or related fields

Experience:

• 2 years of experience in job offered or related occupation.

Special Requirements: 2 years of experience must include work with the following technologies:

• Creating verifications plans from the specifications using Cadence tool eplanner.
• Developing interface UVC components using UVM.
• Creating UVM sequences for complete verification of a module of an ASIC.
• Architecting functional coverage for multiple modules of the design and completed the coverage

monitoring and closure using Cadence tool eManager.

• Utilizing Verilog-OVM Methodology; Scripting Languages, e.g. Perl or Python or Tcl/Tk.
• RTL Design, Coding, Simulation, Verification, and/or Place/Route; Logic Validation.

$194,500 - $202,500 a year

Salary

Worksite: 3315 Scott Blvd., Floor 4, Santa Clara, CA 95054

ApplicantInstructions: Email resume to: [e-mail]. Must specify job code 90541 in reply. EOE.