Senior Mask Layout Design Engineer

NVIDIA; Santa Clara (CA); On-site; USD 124,000 - 230,000; Full time

Job summary

An established industry player is seeking a Senior Mask Layout Design Engineer to join their dynamic team. This role involves performing physical layouts for high-speed mixed-signal circuits and collaborating with engineers on VLSI product integration. The ideal candidate will have extensive experience in mask design and a deep understanding of analog circuit layout concepts. This is a fantastic opportunity to contribute to cutting-edge technology in a diverse and inclusive environment that values creativity and innovation.

Qualifications

• 8+ years of mask design/layout experience required.
• Experience with FinFET technology and tape-out processes preferred.

Responsibilities

• Perform physical layout for mixed-signal functions using Cadence tools.
• Collaborate with engineers for integration in VLSI products.

Skills

Mixed-signal circuit design

High-speed I/O circuits

Analog circuit layout

Teamwork and interpersonal skills

Scripting (Perl, Python, Skill)

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

Cadence tools

Cadence Virtuoso

Calibre/ICV

Job description

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Are you interested in joining our dynamic team? If yes, we are looking for a Senior Mask Layout Design Engineer — someone excited to join a growing, diverse group responsible for high-speed mixed-signal circuit designs.

NVIDIA has reinvented itself over two decades, from pioneering the GPU in 1999 to fueling AI advancements today. Our mission is to amplify human creativity and intelligence.

What You'll Be Doing

• Perform physical layout for mixed-signal functions such as PLLs, high-speed I/O circuits, general I/Os, and ESD structures in advanced CMOS technologies using Cadence tools.
• Collaborate with ASIC and mixed-signal engineers to customize designs for integration in VLSI products, including floor planning, custom layout, and verification against design rules and schematics.

What We Need To See

• Bachelor’s degree in Electrical Engineering or related field; Master’s degree is a plus.
• 8+ years of relevant mask design/layout experience.
• Experience with tape-out processes using FinFET technology, preferably TSMC N5/N4/N3.
• Knowledge of high-speed SerDes/RF layout design and top-level integration is advantageous.
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
• Proficiency with Cadence Virtuoso and experience with DRC and LVS tools like Calibre/ICV.
• Strong teamwork, interpersonal skills, and positive attitude.
• Scripting skills in Perl, Python, or Skill are beneficial.
• Ability to customize DRC and LVS flows.

The salary range is $124,000 to $230,000, based on experience and location. Benefits and equity are included.

NVIDIA values diversity and is an equal opportunity employer. We do not discriminate based on race, religion, gender, or other protected characteristics.