Senior LSF Scheduler Architect - Multi-Cluster HPC

NVIDIA; Massachusetts; Hybrid; USD 184,000 - 357,000; Full time

Job summary

NVIDIA's EDA compute environment relies on advanced LSF internals. We seek a deep specialist to own scheduler behavior, tune mbatchd/mbschd across 15–25 federated cells, and define federation design as the farm grows.

You will collaborate with IaC, CAD, and methodology teams on 500GB+ memory workloads and batch-vs-interactive contention, ensuring scalable scheduling from submission to dispatch.

Qualifications

• BS or MS in Computer Science, Computer Engineering, or equivalent experience.
• 8+ years in HPC or large-scale batch compute, with 5+ years of that on IBM Spectrum LSF.
• Demonstrated depth in LSF internals — you have debugged scheduler behavior beyond what the documentation covers, and you can explain a scheduling cycle from submission to dispatch.
• Hands-on MultiCluster experience in a production, multi-site environment.
• Strong Linux systems fundamentals, system programming languages and scripting in Python, Perl, and shell.

Responsibilities

• Own scheduler behavior across 15–25 federated LSF cells, including mbatchd and mbschd tuning, scheduling cycle analysis, and contention patterns.
• Diagnose MultiCluster forwarding problems — remote queue sizing and cross-cluster pend behavior.
• Set the technical design for cell topology and federation as the farm grows, deciding what belongs in a cell vs. a new one.
• Encode scheduler policy into a config schema that survives MultiCluster integration via IaC.
• Partner with CAD and methodology teams on large-memory workloads and 500GB+ jobs.

Skills

LSF internals

HPC experience

MultiCluster experience

Linux fundamentals

Python

Shell scripting

Perl

Education

BS or MS in Computer Science or Computer Engineering or equivalent

Tools

IBM Spectrum LSF

esub

eexec

elim

submit wrappers

RTM

LSF APIs

Job description

NVIDIA's EDA compute environment relies on advanced LSF internals. We seek a deep specialist to own scheduler behavior, tune mbatchd/mbschd across 15–25 federated cells, and define federation design as the farm grows.

You will collaborate with IaC, CAD, and methodology teams on 500GB+ memory workloads and batch-vs-interactive contention, ensuring scalable scheduling from submission to dispatch.