Senior Low-Power CPU Design & Optimization

Google Inc.; Austin (TX); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Austin, TX is seeking a Low Power Design Methodology and Optimization Engineer to drive advanced power techniques for CPU architectures. You will develop and implement power reduction methods, perform power estimation, and collaborate with RTL, verification, and physical design teams to deliver efficient silicon.

The role requires strong analytical skills, 10 years in low-power design, and experience with Python/C/C++, plus a track record of shaping power management specifications and

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience in CPU low power design and optimization.
• Experience with low-power design (dynamic/ leakage, power estimation/ optimization), data analytics, and profiling.
• Experience in flow automation (Python, C, C++).

Responsibilities

• Develop and implement advanced low power design methodologies for CPU architectures.
• Perform detailed power analysis, estimation, and optimization across various design stages.
• Collaborate with RTL design, verification, and physical design teams to integrate power-saving features.
• Drive the adoption of innovative power reduction techniques and tools.
• Contribute to the definition and validation of power management specifications.

Skills

Low-power design

Data analytics

Profiling

Python

C

C++

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

PTPX

Ansys Power Artist

Synopsys Prime Power RTL

Job description

Google Austin, TX is seeking a Low Power Design Methodology and Optimization Engineer to drive advanced power techniques for CPU architectures. You will develop and implement power reduction methods, perform power estimation, and collaborate with RTL, verification, and physical design teams to deliver efficient silicon.

The role requires strong analytical skills, 10 years in low-power design, and experience with Python/C/C++, plus a track record of shaping power management specifications and