Senior LLM Training Performance & Co-Design Engineer

Google; Sunnyvale (CA); On-site; USD 174,000 - 252,000; Full time

Job summary

Google Sunnyvale is seeking a Senior Performance Co-design Engineer for LLM training to shape future ML accelerators and ensure efficient training across current and future silicon. You will lead hardware/software co-design and performance modeling, collaborating with ML research and compiler teams to optimize training workloads.

You will analyze distributed training bottlenecks in 1P/3P models, build modeling infrastructure and tooling, and influence the roadmap for TPU/Cloud Silicon

Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field or equivalent practical experience.
• 5 years of experience in performance modeling, computer architecture, or hardware/software co-design.
• Experience with programming in C++ or Python.

Responsibilities

• Lead hardware/software co-design and performance modeling for LLM training workloads across current and future generation silicon.
• Analyze distributed training bottlenecks (compute, memory, networking) for massively scaled 1P and 3P models.
• Build and enhance modeling infrastructure, simulators, and performance tooling tailored to distributed ML training.
• Drive data-backed decisions that influence the roadmap for future TPU/Cloud Silicon architectures.
• Work closely with ML research and compiler teams to optimize training algorithms and influence future hardware design.

Skills

performance modeling

computer architecture

hardware/software co-design

C++ or Python

Education

Bachelor's degree

Job description

Google Sunnyvale is seeking a Senior Performance Co-design Engineer for LLM training to shape future ML accelerators and ensure efficient training across current and future silicon. You will lead hardware/software co-design and performance modeling, collaborating with ML research and compiler teams to optimize training workloads.

You will analyze distributed training bottlenecks in 1P/3P models, build modeling infrastructure and tooling, and influence the roadmap for TPU/Cloud Silicon