Senior LLM Serving Performance Co-Design Engineer

Socket.dev; Sunnyvale (CA); On-site; USD 174,000 - 252,000; Full time

Job summary

Google Cloud’s TPU Chip Architecture and Performance Co-design team seeks a Senior Performance Co-Design Engineer to drive LLM serving studies and optimize serving performance on our custom AI silicon. You’ll partner with researchers and hardware teams to balance latency and throughput for emerging models.

Join a team that shapes the frontier of enterprise AI, contributing to the evolution of Google’s ML accelerators and hyperscale infrastructure at scale.

Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
• 5 years of experience in performance modeling/engineering, computer architecture, co-design, or systems engineering.
• Experience programming in C++ or Python.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with hardware/software co-design problems, especially performance analysis and identification at the pre-silicon stage.
• Experience enabling and optimizing large-scale ML models (e.g., LLMs, large embedding models).
• Experience with ML infrastructure, profiling tools, or deep learning inference/serving optimizations.
• Familiarity with accelerator architectures.

Responsibilities

• Conduct comprehensive serving performance studies on (current and emerging) LLMs (1P/3P models).
• Develop and maintain advanced simulation, profiling, and modeling tools to identify bottlenecks, understand key characteristics and project serving workload performance.
• Partner with model researchers, software and hardware teams to co-design architectural improvements tailored to Large Language Model (LLM) inference latency and throughput.
• Drive data-backed decisions that influence the roadmap for future TPU/Cloud Silicon architectures.

Skills

C++

Python

Profiling tools

ML infrastructure

DL inference/serving

Accelerator architectures

Education

Bachelor's degree in CS/EE/CE

Master's degree in CS/EE/CE

PhD in CS/EE/CE

Tools

Profiling tools

ML infrastructure

DL inference/serving

Accelerator architectures

Job description

Google Cloud’s TPU Chip Architecture and Performance Co-design team seeks a Senior Performance Co-Design Engineer to drive LLM serving studies and optimize serving performance on our custom AI silicon. You’ll partner with researchers and hardware teams to balance latency and throughput for emerging models.

Join a team that shapes the frontier of enterprise AI, contributing to the evolution of Google’s ML accelerators and hyperscale infrastructure at scale.