Senior Performance Co-design Engineer, LLM Training

Socket.dev; Sunnyvale (CA); On-site; USD 174,000 - 252,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google Cloud’s TPU Chip Architecture and Performance Co-design team seeks a Senior Performance Engineer in Sunnyvale to optimize AI silicon for large language model training. You will study training workloads for 1P and 3P models, shaping hardware and software architectures for scalable AI.

The role blends architecture, performance modeling, and collaboration across ML research and compiler teams. We offer a path to influence TPU/Cloud Silicon roadmaps, with equity, benefits, and a 15% bonus

Qualifications

• Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field or equivalent practical experience.
• 5 years of experience in performance modeling, computer architecture, or hardware/software co-design.
• Experience with programming in C++ or Python.

Responsibilities

• Lead hardware/software co-design and performance modeling for LLM training workloads across current and future generation silicon.
• Analyze distributed training bottlenecks (compute, memory, networking) for massively scaled 1P and 3P models.
• Build and enhance modeling infrastructure, simulators, and performance tooling tailored to distributed ML training.
• Drive data-backed decisions that influence the roadmap for future TPU/Cloud Silicon architectures.
• Work closely with ML research and compiler teams to optimize training algorithms and influence future hardware design.

Skills

C++

Python

Education

Bachelor's degree or equivalent in CS/EE/CE

Job description

MINIMUM QUALIFICATIONS:

• Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field or equivalent practical experience.
• 5 years of experience in performance modeling, computer architecture, or hardware/software co-design.
• Experience with programming in C++ or Python.

PREFERRED QUALIFICATIONS:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Deep understanding of distributed ML training methodologies (data, tensor, and pipeline parallelism).

ABOUT THE JOB:

Google Cloud’s mission is to make every business successful through AI by combining cutting-edge technology, infrastructure, and talent. AI/ML software engineers in Cloud bridge the gap between pioneering models and a massive product vehicle reaching billions. Our talent density and AI-powered tools drive rapid development, rooted in a culture of empowerment and a bias to action. In this role, you aren’t just building technology; you’re shaping the frontier of enterprise and driving the evolution of advanced models.

The TPU Chip Architecture and Performance Co-design team is at the forefront of optimizing Google's custom AI silicon for next-generation machine learning models. As a Senior Performance Engineer, you will specialize in LLM training studies to shape the hardware and software architectures that will train the world’s most capable AI models. You will analyze training workloads for first-party (1P) and third-party (3P) models to drive the next evolution of Google's custom ML accelerators.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

RESPONSIBILITIES:

• Lead hardware/software co-design and performance modeling for LLM training workloads across current and future generation silicon.
• Analyze distributed training bottlenecks (compute, memory, networking) for massively scaled 1P and 3P models.
• Build and enhance modeling infrastructure, simulators, and performance tooling tailored to distributed ML training.
• Drive data-backed decisions that influence the roadmap for future TPU/Cloud Silicon architectures.
• Work closely with ML research and compiler teams to optimize training algorithms and influence future hardware design.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $174000 - $252000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google [https://www.google.com/about/careers/applications/benefits/].