Senior LLM Efficiency Architect: Model Systems Co-Design

Nvidia Corporation in; Santa Clara (CA); Hybrid; USD 184,000 - 357,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Santa Clara, CA is seeking a Senior DL Performance Efficiency Architect (Finance) to lead the strategy and execution for making large language models more efficient from research to deployment. You will drive cross-layer optimization, collaborate with researchers and hardware teams, and shape how future models and platforms are designed for practical compute, memory, power, and cost constraints.

The role requires hands-on leadership, deep knowledge of LLM workloads, and a track record

Qualifications

• MS or PhD in CS/EE/CE or equivalent experience.
• 5+ years in AI systems, model architecture, or performance optimization.
• Strong understanding of LLM architectures, training and inference workloads.
• Proven ability to lead complex optimization projects from concept to production.
• Experience with roofline modeling, benchmarking and hardware-aware optimization.

Responsibilities

• Lead cross-layer efforts to improve the efficiency of large language models across model architecture, training and inference systems.
• Analyze how LLM workloads map to GPUs, memory systems, interconnects, and distributed infrastructure, and identify opportunities for model-system-hardware co-design.
• Establish a measurement-driven efficiency roadmap and lead projects from early investigation through production deployment.
• Partner with model researchers, systems engineers, compiler and kernel developers, and hardware architects to influence future model, software, and hardware roadmaps.

Skills

AI systems

Model architecture

Computer architecture

Performance optimization

High-performance computing

Education

MS or PhD in CS/EE/CE or equivalent

Job description

NVIDIA in Santa Clara, CA is seeking a Senior DL Performance Efficiency Architect (Finance) to lead the strategy and execution for making large language models more efficient from research to deployment. You will drive cross-layer optimization, collaborate with researchers and hardware teams, and shape how future models and platforms are designed for practical compute, memory, power, and cost constraints.

The role requires hands-on leadership, deep knowledge of LLM workloads, and a track record