Senior DL Performance Efficiency Architect

NVIDIA; Santa Clara (CA); Hybrid; USD 184,000 - 357,000; Full time

Job summary

NVIDIA is seeking a strong technical leader to drive a unified strategy for making LLMs more efficient from research through deployment. You will lead a multidisciplinary effort combining model ideas, systems expertise and hardware awareness to deliver scalable improvements while managing compute, memory, power and cost constraints.

The role requires hands-on leadership across model, software and hardware roadmaps, with a focus on measurable throughput and cost-per-token improvements.

Qualifications

• Advanced degree or equivalent in CS/EE or related field.
• Strong background in AI systems and model architectures.
• Proven track record in performance optimization and HPC.

Responsibilities

• Lead cross-layer efforts to improve LLM efficiency across architecture, training and inference.
• Analyze workloads mapping to GPUs, memory, interconnects and distributed systems.
• Establish measurement-driven roadmaps from research to production.
• Collaborate with researchers, engineers, compilers and hardware architects.

Skills

AI systems

Model architecture

High-performance computing

Hardware awareness

Performance optimization

Education

MS or PhD degree or equivalent

Job description

NVIDIA’s accelerated computing platform is enabling the generational improvements in large language models, while the scale and complexity of these models are creating new challenges in computational efficiency. We are seeking a strong technical leader to drive a unified strategy for making LLMs more efficient from research through deployment. This role will bring together model innovation, systems expertise, and hardware awareness to ensure that new capabilities can be delivered within practical constraints of compute, memory, power, and cost. You will lead a multidisciplinary effort, establish the technical direction for LLM efficiency, and help shape how future models and computing platforms are designed together. The ideal candidate is a hands‑on engineer who enjoys finding fundamental bottlenecks, challenging conventional boundaries between disciplines, and turning research ideas into scalable, real‑world improvements.

What you will be doing:

• Lead cross-layer efforts to improve the efficiency of large language models across model architecture, training and inference systems.

• Analyze how LLM workloads map to GPUs, memory systems, interconnects, and distributed infrastructure, and identify opportunities for model‑system‑hardware co‑design.

• Establish a measurement‑driven efficiency roadmap and lead projects from early investigation through production deployment.

• Partner with model researchers, systems engineers, compiler and kernel developers, and hardware architects to influence future model, software, and hardware roadmaps.

What we need to see:

• MS or PhD degree, or equivalent experience, in Computer Science, Electrical Engineering, Computer Engineering, or a related field.

• 5+ years of relevant experience in AI systems, model architecture, computer architecture, high‑performance computing, or performance optimization.

• Strong understanding of LLM architectures, training and inference workloads, and the tradeoffs between model quality, computational cost, memory footprint, latency, throughput, and power.

• Strong background in performance analysis, roofline modeling, workload characterization, benchmarking, and hardware‑aware optimization.

• Proven ability to provide technical leadershipand drive complex optimization projects from concept to production.

Ways to Stand Out from the Crowd:

• A track record of delivering measurable improvement throughput, cost per token, energy per token, memory efficiency, or time to train.

• A first‑principles - measure, model, optimize, and deliver - approach to improving LLM efficiency.

• Familiarity with low‑precision computation, quantization, sparsity, Mixture‑of‑Experts, long‑context inference, and speculative decoding.

• Experience co‑designing model architectures with training, inference, compiler, or hardware constraints.

• Experience influencing accelerator, system, or datacenter architecture based on future AI workload requirements.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward‑thinking and hardworking people in the world working for us. Are you creative architect interested in pushing silicon to its highest performance and efficiency ? If so, we want to hear from you! Come, join our DL Architecture team and help build the real‑time, cost‑effective AI computing platform driving our success in this exciting and quickly growing field. #LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 7, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.