Senior Lead Design Engineer

191 Altera Corporation; San Jose (CA); On-site; USD 232,000 - 330,000; Full time

Job summary

Altera is seeking a Senior Lead Design Engineer in San Jose to provide hands-on technical leadership across FPGA, programmable SoC, and infrastructure-class subsystems. You will drive architecture, RTL design, verification, and post-silicon readiness, translating complex product requirements into scalable, high-performance digital solutions.

You will mentor teams, define interfaces, and collaborate with architecture, CAD, firmware, and software groups to ensure architectural integrity and timely

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 15+ years of experience in FPGA/ASIC/SoC or semiconductor product development.
• Proven leadership delivering complex digital subsystems from architecture through post-silicon.

Responsibilities

• Lead architecture, microarchitecture, and RTL development for FPGA, SoC, and subsystems.
• Define requirements, interfaces, and implementation plans aligning hardware, firmware, software, and validation.
• Drive tradeoffs across performance, power, area, latency, and schedule; mitigate execution risk.
• Own critical blocks through RTL to post-silicon validation and bring-up.
• Establish reusable IP, coding standards, and quality methodologies to improve velocity and predictability.
• Collaborate across architecture, RTL, verification, physical design, CAD, firmware, and software teams.

Skills

RTL design

SystemVerilog

FPGA architecture

Digital subsystems

Leadership

Cross-functional collaboration

Education

Electrical Engineering degree

Advanced degree preferred

Tools

Python scripting

Synthesis tools

Job description

About the Role

Altera is seeking a Senior Lead Design Engineer to provide hands-on technical leadership for the architecture, design, and delivery of next-generation FPGA and programmable SoC solutions. This is a senior individual-contributor/technical leadership role for an engineer who can influence technical direction across complex subsystems, product generations, and global engineering teams. In this role, you will lead the definition and implementation of high-performance digital logic and reusable IP for programmable devices and platform solutions. You will translate product and system requirements into scalable architectures, drive key design decisions, and guide execution from early concept through RTL delivery, validation, and product readiness. The successful candidate will bring deep experience in complex ASIC, SoC, or FPGA development, a rigorous approach to design quality, and the ability to deliver impactful solutions for data center, networking, AI, and edge applications.

Responsibilities

• Lead architecture, microarchitecture, and RTL development for complex FPGA, programmable SoC, and infrastructure-class subsystems, with emphasis on high-throughput datapaths, connectivity, interconnect, memory access, or programmable acceleration.
• Define technical requirements, interfaces, architectural specifications, and implementation plans that align hardware, firmware, software, validation, and product objectives.
• Drive technical tradeoffs across performance, power, area, latency, bandwidth, reliability, scalability, cost, and schedule; use data and analysis to identify and mitigate execution risk.
• Own critical blocks and subsystems through the full development lifecycle, including RTL implementation, synthesis, integration, verification support, timing closure, bring-up, performance characterization, and issue resolution.
• Establish and scale reusable design IP, coding standards, automation, and quality methodologies that improve engineering velocity, portability, predictability, and first-pass success.
• Partner with architecture, design verification, physical design, DFT, CAD, firmware, software, emulation, FPGA prototyping, board, and post-silicon teams to ensure architectural intent is maintained through product delivery.
• Lead resolution of complex cross-functional design and system issues, including root-cause analysis, debug strategy, and technical decision-making.
• Provide technical mentorship and design leadership across teams; raise the engineering bar through architecture reviews, code reviews, and constructive technical guidance.
• Influence engineering roadmaps and collaborate with internal teams and external partners on IP, tools, and technology choices that strengthen Altera’s programmable technology portfolio.

What You Will Bring

You are a hands-on design leader who pairs strong technical depth with broad systems perspective. You bring sound engineering judgment, a high bar for quality, and a collaborative leadership style that helps teams solve complex problems and deliver differentiated programmable solutions. You are motivated by enabling customers to create what is next with Altera technology.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $231,500 - $330,000 USD We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications

• Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, with 15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development; advanced degree preferred.
• Demonstrated technical leadership delivering complex digital subsystems or products from system architecture and microarchitecture through RTL, verification, integration, implementation, and post-silicon or hardware validation.
• Deep hands-on expertise in Verilog and/or SystemVerilog RTL design, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation-aware design practices.
• Proven experience with high-performance digital architectures, such as networking or packet-processing datapaths, offload or acceleration engines, PCIe/CXL, Ethernet, DDR/HBM memory subsystems, high-speed interfaces, or on-chip interconnect.
• Strong understanding of performance, power, area, timing, bandwidth, latency, congestion, and reliability tradeoffs in advanced digital systems.
• Experience leading design execution across multiple functional blocks or chip-level integration, including planning, risk management, schedule alignment, and technical prioritization.
• Demonstrated ability to collaborate and influence across architecture, RTL, verification, physical design, CAD, firmware/software, system validation, and product engineering organizations.
• Strong written and verbal communication skills, with the ability to clearly communicate architecture, design intent, technical risks, and recommendations to diverse audiences.

Preferred Qualifications

• Experience in FPGA architecture, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
• Experience building or maintaining reusable design IP deployed across multiple products, programs, or technology nodes.
• Experience with FPGA prototyping, emulation, silicon bring-up, post-silicon debug, or performance optimization.
• Proficiency in scripting and workflow automation using Python, Tcl, Perl, or shell.
• Experience leading teams or serving as a senior technical mentor in a matrixed engineering environment.
• Record of innovation through patents, publications, standards contributions, or technical thought leadership.

Job Type

Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.