Senior IC Design Engineer — High-Performance Cores & Equity

Broadcom Inc.; Irvine (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

401(K) with company match

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Paid holidays

Paid vacation

Job summary

Broadcom Inc. is seeking a motivated engineer for the Central Engineering Team in Irvine to develop standard cells and custom design solutions powering AI compute cores and CPUs. You will design digital high‑performance blocks and drive timing closure for optimal PPA.

The role requires 5–10 years of hands-on Place and Route experience, strong communication, and collaboration skills. A Bachelor's in Engineering with 5+ years experience is expected; advanced degrees are a plus.

Qualifications

• Bachelor's and 5+ years of related experience; Master’s or PhD in Engineering is a plus.
• Strong understanding of physical implementation.
• Experience with advanced semiconductor technologies.
• Experience implementing low power and high‑performance cores.

Responsibilities

• Layout design of digital high-performance blocks.
• Timing closure of the blocks with best PPA (power/performance/area).
• Debug LVS/DRC/ERC errors with verification tool.
• Analyze trade-offs and performance implications of different cell architectures.
• Collaborate with design and layout engineers to optimize layout for area and performance.
• Work with CAD, packaging and foundry teams in resolving layout and/or verification issues.

Skills

Physical implementation knowledge

Advanced semiconductor technologies

Low power design

Cross-functional collaboration

Data-driven decisions

Place and route tools

Education

Bachelor's degree in Engineering

Master's or PhD in Engineering (plus)

Tools

Place and Route tools

CAD tools

Job description

Broadcom Inc. is seeking a motivated engineer for the Central Engineering Team in Irvine to develop standard cells and custom design solutions powering AI compute cores and CPUs. You will design digital high‑performance blocks and drive timing closure for optimal PPA.

The role requires 5–10 years of hands-on Place and Route experience, strong communication, and collaboration skills. A Bachelor's in Engineering with 5+ years experience is expected; advanced degrees are a plus.