Senior High-Speed PCB Layout Engineer for Space Systems

Arraylabs.Io; Redwood City (CA); On-site; USD 130,000 - 170,000; Full time

Job summary

Array Labs seeks a Senior High-Speed PCB Layout Engineer to own the physical implementation of high-speed digital and mixed-signal electronics in Altium. You will translate schematics into layouts, define stack-ups and impedance targets, and ensure robust signal integrity and power integrity for space-bound hardware.

You will work closely with electrical design, firmware, mechanical, and test engineers to drive layout constraints, reviews, and manufacturing releases, with emphasis on de-risking

Qualifications

• BS in Electrical Engineering or related field; 4+ years in relevant experience.
• Experience in PCB layout, fabrication, and release of high-speed digital/mixed-signal electronics.
• Strong signal integrity and power integrity focus.

Responsibilities

• Own high-speed PCB layout from initial placement through manufacturing release in Altium.
• Define stack-ups, impedance targets, length-matching constraints, and reference plane strategies.
• Translate schematic intent into layouts meeting SI/PI requirements across domains.
• Collaborate with design, firmware, mechanical, and test teams to develop constraints and de-risk first-spin.
• Drive DFM/DFT considerations with fabrication/assembly partners and release artifacts.

Skills

High-speed layout

Team collaboration

Self-motivation

Communication skills

Education

B.S. in Electrical Engineering

Tools

Altium Designer

Allegro

OrCAD

Ansys SIwave

Keysight Power Analyzer

HyperLynx

Sigrity

Job description

Array Labs seeks a Senior High-Speed PCB Layout Engineer to own the physical implementation of high-speed digital and mixed-signal electronics in Altium. You will translate schematics into layouts, define stack-ups and impedance targets, and ensure robust signal integrity and power integrity for space-bound hardware.

You will work closely with electrical design, firmware, mechanical, and test engineers to drive layout constraints, reviews, and manufacturing releases, with emphasis on de-risking