Senior High-Speed PCB Design Engineer (800G/1.6T)

Arista Networks; Santa Clara (CA); On-site; USD 133,000 - 180,000; Full time

Job summary

Arista Networks is seeking an experienced Hardware Design Engineer to advance high-speed PCB layouts for 800G/1.6T transceivers and next-generation networking platforms. You will collaborate with cross-functional teams across hardware design, SI, PI, mechanical, and manufacturing to drive end-to-end design and development of state-of-the-art networking solutions.

Responsibilities include impedance-controlled routing for 112G/224G PAM4, dense multi-layer stack-ups, and robust PDN/thermal

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field.
• 10+ years of relevant hardware engineering experience.
• Proven experience designing networking hardware, particularly involving 100G/200G PAM4 Ethernet switching.
• Direct experience in high-speed optical transceiver PCB layout (800G and/or 1.6T preferred).
• Expertise with 112G / 224G PAM4 routing and channel optimization.
• Advanced proficiency in Cadence Allegro and Sigrity.
• Experience designing 20+ layer boards with 50G+ signals.
• Hands‑on experience with sequential lamination, HDI, ultra‑low‑loss materials.
• Experience in multi-phase DC/DC layout for high-current, high transient loads.
• Strong manufacturing knowledge including DFM, DFA, and DFT for 30+ layer rigid and rigid-flex boards.
• Demonstrated success taking products from concept through mass production.

Responsibilities

• High-Speed Layout & Routing for 112G/224G SerDes, PCIe Gen 5/6, DDR4/5/6.
• Design and route high-speed differential pairs with impedance control.
• Execute dense BGA fan-out for large ASICs and FPGAs.
• Design and layout boards supporting high-bandwidth optical transceivers (QSFP-DD, OSFP, OSFP-XD).
• Route 112G / 224G PAM4 channels between switch ASICs and optical modules.
• Define insertion loss budgets and ensure IEEE compliance.
• Optimize breakout routing beneath high-density optical cages.
• Implement via stub mitigation including backdrilling.
• Manage ground reference continuity, EMI, and return path near connectors.
• Consider thermal dissipation in layout planning (20W–30W+).
• Design multi-layer stack-ups (20–30+ layers).
• Collaborate with SI teams on simulations.
• Design robust PDNs for high-current ASICs.
• Coordinate mechanical constraints with enclosure and airflow.
• Define backdrilling parameters and impedance specs.
• Review external routing to ensure quality and schedule.

Skills

High-speed PCB design

Signal integrity

Power integrity

Thermal design

HDI materials

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Cadence Allegro

Sigrity

Job description

Arista Networks is seeking an experienced Hardware Design Engineer to advance high-speed PCB layouts for 800G/1.6T transceivers and next-generation networking platforms. You will collaborate with cross-functional teams across hardware design, SI, PI, mechanical, and manufacturing to drive end-to-end design and development of state-of-the-art networking solutions.

Responsibilities include impedance-controlled routing for 112G/224G PAM4, dense multi-layer stack-ups, and robust PDN/thermal