Senior PCB Design Engineer

Arista Networks; Santa Clara (CA); On-site; USD 133,000 - 180,000; Full time

Job summary

Arista Networks is seeking an experienced Hardware Design Engineer to advance high-speed PCB layouts for 800G/1.6T transceivers and next-generation networking platforms. You will collaborate with cross-functional teams across hardware design, SI, PI, mechanical, and manufacturing to drive end-to-end design and development of state-of-the-art networking solutions.

Responsibilities include impedance-controlled routing for 112G/224G PAM4, dense multi-layer stack-ups, and robust PDN/thermal

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field.
• 10+ years of relevant hardware engineering experience.
• Proven experience designing networking hardware, particularly involving 100G/200G PAM4 Ethernet switching.
• Direct experience in high-speed optical transceiver PCB layout (800G and/or 1.6T preferred).
• Expertise with 112G / 224G PAM4 routing and channel optimization.
• Advanced proficiency in Cadence Allegro and Sigrity.
• Experience designing 20+ layer boards with 50G+ signals.
• Hands‑on experience with sequential lamination, HDI, ultra‑low‑loss materials.
• Experience in multi-phase DC/DC layout for high-current, high transient loads.
• Strong manufacturing knowledge including DFM, DFA, and DFT for 30+ layer rigid and rigid-flex boards.
• Demonstrated success taking products from concept through mass production.

Responsibilities

• High-Speed Layout & Routing for 112G/224G SerDes, PCIe Gen 5/6, DDR4/5/6.
• Design and route high-speed differential pairs with impedance control.
• Execute dense BGA fan-out for large ASICs and FPGAs.
• Design and layout boards supporting high-bandwidth optical transceivers (QSFP-DD, OSFP, OSFP-XD).
• Route 112G / 224G PAM4 channels between switch ASICs and optical modules.
• Define insertion loss budgets and ensure IEEE compliance.
• Optimize breakout routing beneath high-density optical cages.
• Implement via stub mitigation including backdrilling.
• Manage ground reference continuity, EMI, and return path near connectors.
• Consider thermal dissipation in layout planning (20W–30W+).
• Design multi-layer stack-ups (20–30+ layers).
• Collaborate with SI teams on simulations.
• Design robust PDNs for high-current ASICs.
• Coordinate mechanical constraints with enclosure and airflow.
• Define backdrilling parameters and impedance specs.
• Review external routing to ensure quality and schedule.

Skills

High-speed PCB design

Signal integrity

Power integrity

Thermal design

HDI materials

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Cadence Allegro

Sigrity

Job description

Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges.

At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation.

Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do.

Job Description

Who You’ll Work With

Working closely with cross-functional teams including Hardware Design, Signal Integrity (SI), Power Integrity (PI), Mechanical Engineering, Thermal Engineering, and Manufacturing, our engineers innovate on system architectures and ultra-high-speed PCB designs to deliver state-of- the-art networking platforms.

What You'll Do

Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in enterprise campuses, hyperscale datacenters, and next-generation AI clusters. The team is responsible for end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments — including optical interface platforms up to 800G and 1.6T.

Core Responsibilities

High-Speed Layout & Routing

Implement complex routing for advanced interfaces such as 112G/224G SerDes, PCIe Gen 5/6, DDR4/5/6

Design and route high-speed differential pairs with tight skew and impedance control

Execute dense BGA fan-out for high-pin-count ASICs and FPGAs

Optical Transceiver PCB Layout (800G / 1.6T)

Design and layout boards supporting high-bandwidth optical transceivers (QSFP-DD, OSFP, OSFP-XD or equivalent)

Route 112G / 224G PAM4 electrical channels between switch ASICs and optical modules

Define insertion loss budgets and coordinate with SI engineers to meet IEEE compliance requirements

Optimize breakout routing beneath high-density optical cages

Implement via stub mitigation strategies including backdrilling for ultra-high-speed signal paths

Manage ground reference continuity, EMI control, and return path integrity near optical connectors

Consider thermal dissipation (20W–30W+ modules) in layout planning

Impedance Control & Signal Integrity

Design advanced multi-layer stack-ups (20–30+ layers)

Calculate impedance profiles and ensure low-reflection, low-crosstalk performance

Collaborate with SI teams on channel modeling and pre-/post-layout simulations

Power Integrity (PI) Optimization

Design robust Power Distribution Networks (PDNs) for high-current ASICs

Layout multi-phase DC/DC converters for high transient loads

Strategically place decoupling capacitors to ensure wideband impedance stability

Thermal &Mechanical Coordination

Integrate thermal vias, heat sink attachments, and high-conductivity materials

Coordinate mechanical constraints such as enclosure, airflow, and structural limitations

Ensure proper placement and structural integration of optical cages

Advanced Fabrication Deliverables

Define backdrilling parameters and impedance specifications

Ensure compliance with DFM, DFA, and DFT requirements

Support boards through fabrication, assembly, and production ramp

Library & Feasibility Ownership

Create and maintain high-density component footprints (e.g., large BGAs, optical module connectors)

Participate in new product feasibility studies

Develop detailed routing guidelines and work packages for layout partners

Review external placement and routing work to ensure quality and schedule adherence

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field

10+ years of relevant hardware engineering experience

Proven experience designing networking hardware, particularly involving 100G/200G PAM4 Ethernet switching

Direct experience in high-speed optical transceiver PCB layout (800G and/or 1.6T preferred)

Expertise with 112G / 224G PAM4 routing and channel optimization

Advanced proficiency in Cadence Allegro and Sigrity

Experience designing 20+ layer boards with 50G+ signals

Hands‑on experience with sequential lamination, HDI, ultra‑low‑loss materials

Experience in multi-phase DC/DC layout for high-current, high transient loads

Strong manufacturing knowledge including DFM, DFA, and DFT for 30+ layer rigid and rigid-flex boards

Demonstrated success taking products from concept through mass production

Compensation Information

The new hire base pay for this role has a salary range of $133,000 to $180,000.Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Arista’s Sales Incentive Plan, which pays commissions calculated as a percentage of eligible sales. US-based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location.

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Additional Information

All your information will be kept confidential according to EEO guidelines.

Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.