Senior HBM Custom Layout Architect

Micron Technology, Inc.; Richardson (TX); On-site; USD 150,000 - 323,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Vision plan

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking a Custom Layout Architecture Engineer to guide HBM architecture decisions from concept to tapeout.

You will collaborate with design, architecture, process, verification, and product teams to optimize performance, power, area, routability, and manufacturability for AI accelerators, HPC, and data centers. The role requires strong experience in semiconductor layout, analog/digital/mixed-signal blocks, and proficiency with Cadence Virtuoso and Calibre, with a focus

Qualifications

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related technical field.
• 4+ years of semiconductor physical layout experience with analog, digital, or mixed-signal blocks.
• Experience converting schematics into manufacturable layouts and completing physical verification.
• Ability to explain layout constraints and tradeoffs to design, architecture, and cross-functional teams.

Responsibilities

• Assess HBM architecture choices through layout feasibility, floorplanning, and performance, power, and area analysis
• Lead custom layout and full-chip integration for analog, mixed-signal, digital, and memory blocks
• Resolve antenna, latch-up, ESD, electromigration, IR drop, routability, and power-delivery constraints
• Complete DRC/LVS, parasitic extraction, post-layout validation, and tapeout support using industry-standard EDA tools
• Build scripts and automation that improve layout quality, verification, and design-cycle time

Skills

Semiconductor layout

Analog/digital/mixed-signal layouts

Layout optimization

Cross-team communication

Education

Bachelor's degree in EE or related

Master's degree in EE or microelectronics

Tools

Cadence Virtuoso VLE/VXL

Siemens Calibre DRC/LVS

Job description

Micron Technology, Inc. is seeking a Custom Layout Architecture Engineer to guide HBM architecture decisions from concept to tapeout.

You will collaborate with design, architecture, process, verification, and product teams to optimize performance, power, area, routability, and manufacturability for AI accelerators, HPC, and data centers. The role requires strong experience in semiconductor layout, analog/digital/mixed-signal blocks, and proficiency with Cadence Virtuoso and Calibre, with a focus