Senior Hardware Validation Engineer – Python & Networking

Cisco; United States; On-site; USD 150,000 - 190,000; Full time

Job summary

Cisco is seeking a Senior Hardware Validation Engineer to join the Silicon One initiative. You will help validate high-performance silicon software and hardware validation frameworks across hardware, simulation, and CI/CD environments.

You will apply Python/test-automation, lead end-to-end tests, and collaborate with silicon, SDK, and architecture teams to ensure reliable line-rate silicon and early defect detection.

Qualifications

• 7–12 years of experience in software development.
• Strong Python and test automation (pytest, CI).
• Networking fundamentals: L2/L3, ACLs, QoS/meters, tunnels, multicast, and packet forwarding concepts.
• System design and architecture experience with scalable software components.
• Comfort working close to hardware: lab boards, SerDes, port bring-up, long-running HW regressions.

Responsibilities

• Develop and enhance the core hardware validation framework for Cisco Silicon One ASICs.
• Design and automate end-to-end validation tests across hardware, simulation, and CI/CD environments.
• Build scalable, reliable test frameworks using Python/pytest.
• Validate next-generation networking features including packet processing, QoS, ACLs, warm boot, and multi-device topologies.
• Collaborate with silicon, SDK, and architecture teams to ensure coverage and early defect detection.
• Own hardware smoke and regression testing to maintain quality across releases.
• Debug complex hardware and software issues and drive root-cause analysis.

Skills

Python

Test automation

Networking fundamentals

System design

Hardware bring-up

CI/CD

pytest

Tools

CI/CD pipelines

Job description

Cisco is seeking a Senior Hardware Validation Engineer to join the Silicon One initiative. You will help validate high-performance silicon software and hardware validation frameworks across hardware, simulation, and CI/CD environments.

You will apply Python/test-automation, lead end-to-end tests, and collaborate with silicon, SDK, and architecture teams to ensure reliable line-rate silicon and early defect detection.