Senior Hardware Emulation Engineer, Google

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google LLC in Sunnyvale, CA is seeking a Senior Hardware Emulation Engineer to advance AI/ML hardware acceleration and TPU architecture integration. You will develop and verify complex emulation systems, collaborate with firmware and software teams, and drive pre-silicon validation and lab bring-up for large-scale ASIC projects.

The role emphasizes building and debugging RTL models on emulation platforms, bringing up high-speed interfaces, and shaping verification methodologies for efficient

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
• 8 years of experience with hardware emulation systems (e.g., Palladium, ZeBu, Veloce), model compilation, runtime performance optimization, and methodology enhancements.
• Experience with Verilog/SystemVerilog, C/C++, Python or Perl/TCL scripting, CI/CD automation, and debugging high-speed protocols (e.g., PCIe, HBM, DDR5, UCIe, Ethernet) using waveform tools (e.g., Verdi, SimVision/Indago, GDB).
• Experience interfacing with emulation EDA vendors and internal infrastructure teams to triage compiler, tool, and platform issues and gauge emulation throughput.

Responsibilities

• Build, compile, and debug full-chip and multi-die System-on-Chip (SoC) RTL models and tests on hardware emulation platforms.
• Bring up external interfaces (e.g., PCIe, HBM, DDR5, UCIe, Ethernet, USB) on emulation platforms using transactors, Accelerated VIPs, and speed bridges.
• Explore verification and emulation methodologies, gather feedback and implement new emulation workflows and CI/CD automation.
• Partner with firmware, system software, and post-silicon validation teams to drive pre-silicon hardware/software co-verification, shift-left software bring-up, and silicon bug reproduction on emulation.
• Support emulation and software team members in debugging hardware, tooling, compile, and runtime issues, and act as a technical interface to emulation vendors.

Skills

Hardware emulation

Verilog/SystemVerilog

C/C++

Scripting

High-speed protocols

CI/CD automation

Debugging tools

Education

Bachelor’s degree in Electrical Engineering/Computer Engineering or related

Master’s degree or PhD preferred

Tools

Palladium

ZeBu

Veloce

Job description

Senior Hardware Emulation Engineer, Google

Share Senior Hardware Emulation Engineer, Google

Google Sunnyvale, CA, USA

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
• 8 years of experience with hardware emulation systems (e.g., Palladium, ZeBu, Veloce), model compilation, runtime performance optimization, and methodology enhancements.
• Experience with Verilog/SystemVerilog, C/C++, Python or Perl/TCL scripting, CI/CD automation, and debugging high-speed protocols (e.g., PCIe, HBM, DDR5, UCIe, Ethernet) using waveform tools (e.g., Verdi, SimVision/Indago, GDB).
• Experience interfacing with emulation EDA vendors and internal infrastructure teams to triage compiler, tool, and platform issues and guage emulation throughput.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience across three or more SoC projects/tapeout cycles.
• Experience architecting and bringing up advanced emulation testbench environments (e.g., Transactors/Accelerated VIPs, SpeedBridges/Speed Adapters, Hybrid/Virtual Host platforms, and In-Circuit Emulation).

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will help develop and maintain emulation infrastructure, tools, and workflow methodologies supporting ASIC projects. You will help create ASICs representing a significant investment in time and money, and a successful prototyping campaign helps to ensure success of these critical projects. However, as designs continue to increase in size and complexity, emulation becomes even more important in meeting verification and bring-up milestones. You will provide excellent emulation infrastructure and methodologies essential to support these projects.

You will work directly with other emulation team members as well as designers, verification engineers, and software teams. You will compile complex projects targeting our platforms, bring up high-speed interfaces, debug issues across design and infrastructure, and help drive pre-silicon and lab bring-up and validation of our ASIC systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

• Build, compile, and debug full-chip and multi-die System-on-Chip (SoC) RTL models and tests on hardware emulation platforms.
• Bring up external interfaces (e.g., PCIe, HBM, DDR5, UCIe, Ethernet, USB) on emulation platforms using transactors, Accelerated VIPs, and speed bridges.
• Explore verification and emulation methodologies, gather feedback and implement new emulation workflows and CI/CD automation.
• Partner with firmware, system software, and post-silicon validation teams to drive pre-silicon hardware/software co-verification, shift-left software bring-up, and silicon bug reproduction on emulation.
• Support emulation and software team members in debugging hardware, tooling, compile, and runtime issues, and act as a technical interface to emulation vendors.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.