Senior GPU Driver & Memory Architect

HP Inc.; Palo Alto (CA); On-site; USD 147,000 - 231,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Long term/short term disability

Employee assistance program

Flexible spending account

Life insurance

Parental leave (4-12 weeks)

Paid holidays

Flexible vacation and sick leave

Job summary

HP Inc. in California seeks a GPU Driver & Memory Management Architect to lead driver architecture for memory management across CPU/GPU/NPU, enabling efficient shared memory use. You will own the architecture and collaborate across OS drivers and hardware teams to scale AI workloads.

The role emphasizes performance optimization and cross-organization leadership, with strong hardware design and software toolchain experience required.

Qualifications

• Four-year or graduate degree in electrical engineering or related field.
• Typically 10+ years of work experience in electrical design and tools, software packages, architecture of electronic hardware.

Responsibilities

• Architect driver-level memory management (DVMT, shared memory models, WDDM).
• Enable dynamic memory allocation across GPU, CPU, and NPU.
• Optimize iGPU performance for AI + graphics hybrid workloads.
• Define OS-driver contracts (Windows/Linux).
• Diagnose and resolve memory-related performance bottlenecks.
• Partner with IHVs on driver capabilities and requirements.

Skills

Memory GPU design

Electrical Engineering

Computer Science

Debugging

FPGA

Hardware Architecture

Schematic Capture

Simulations

MATLAB

OS-driver contracts

Education

Four-year or Graduate Degree in Electrical Engineering, or commensurate work experience

Tools

MATLAB

Job description

HP Inc. in California seeks a GPU Driver & Memory Management Architect to lead driver architecture for memory management across CPU/GPU/NPU, enabling efficient shared memory use. You will own the architecture and collaborate across OS drivers and hardware teams to scale AI workloads.

The role emphasizes performance optimization and cross-organization leadership, with strong hardware design and software toolchain experience required.