Senior FPGA Signal Processing Engineer – Modem/DSP

L3Harris

City of Rochester (NY)

On-site

USD 93,000 - 172,000

Full time

4 days ago
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Benefits offered by this job

Sign-on bonus
Health insurance
401(k) match
Education assistance
Parental leave
Paid time off
Company-paid holidays

Job summary

L3Harris is seeking a signal-processing focused FPGA engineer to design, verify, and test modem and DSP based FPGA firmware for radio communications. You will architect FPGA solutions, develop verification plans, and work with cross-functional teams in a security-sensitive environment.

The role requires RTL/VHDL background, SystemVerilog verification, and experience with FPGA vendor tools (Vivado/Quartus/Libero). A US Secret Clearance is preferred.

Qualifications

  • Bachelor's Degree with 6 years prior experience or Graduate Degree with 4 years prior experience.
  • In lieu of a degree, minimum of 10 years of prior related experience.
  • Experience with RTL development and FPGA verification methodologies.

Responsibilities

  • Analyze system requirements and architect FPGA based processing solutions.
  • Implement modem/DSP circuits in FPGA or equivalent ASIC.
  • Design, verify and test FPGA firmware for radio communications systems.
  • Develop verification/test plans and use UVM.
  • Prepare design and implementation reviews and brief customers.

Skills

RTL development
VHDL
SystemVerilog
FPGA design
Modem design
DSP concepts
Python scripting
TCL scripting
Linux development
US Secret Clearance

Education

Bachelor's Degree
Graduate Degree
10+ years related experience in lieu of degree

Tools

MatLab
Simulink
Vivado
Quartus
Libero

Job description

L3Harris is seeking a signal-processing focused FPGA engineer to design, verify, and test modem and DSP based FPGA firmware for radio communications. You will architect FPGA solutions, develop verification plans, and work with cross-functional teams in a security-sensitive environment.

The role requires RTL/VHDL background, SystemVerilog verification, and experience with FPGA vendor tools (Vivado/Quartus/Libero). A US Secret Clearance is preferred.

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