Senior FPGA & SDR Modem Architect

Axon; Boston (MA); Hybrid; USD 141,000 - 226,000; Full time

Benefits offered by this job

Competitive salary and 401k

Discretionary paid time off

Paid parental leave

Fitness programs

Mental wellness support

Snacks in the office

Job summary

Axon seeks a Senior FPGA/RTL Designer to own DSP-friendly FPGA implementations, RTL, and verification for SDR/OFDM modems. You will model in MATLAB/Simulink, generate RTL from Simulink, and ensure timing-closed implementations on Zynq-based platforms. The role blends software, firmware, RF, and hardware teams.

Based in Boston or Scottsdale with a hybrid schedule, you’ll collaborate across departments, mentor engineers, and drive design quality with rigorous verification and documentation.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering.
• 6+ years FPGA/RTL design experience.
• Proficiency in VHDL/Verilog/SystemVerilog.
• Strong Vivado experience.
• Proficiency with MATLAB/Simulink for algorithms.
• Experience with AXI4/AXI4-Stream, DMA, and clock-domain crossing.
• Strong RTL verification and testbench development.
• Excellent documentation and communication.

Responsibilities

• Research, model, and implement industry-leading SDR and digital communications algorithms for products in our mesh and connected-device portfolio.
• Develop floating- and fixed-point behavioral reference models in MATLAB/Simulink and validate performance against requirements.
• Generate and integrate RTL from Simulink using HDL Coder, and write VHDL/Verilog where needed.
• Implement designs in Vivado from synthesis to timing closure and refine constraints.
• Architect and implement on-chip interfaces (AXI4/AXI4-Stream, DMA) and CDC logic.
• Build and maintain verification: simulators, RTL testbenches, regression suites.
• Collaborate with firmware to define hardware/software interfaces and register maps.
• Mentor junior engineers and contribute to model-based design practices.

Skills

RTL design

VHDL/Verilog

Vivado

MATLAB/Simulink

DSP fundamentals

AXI4/AXI4-Stream

FPGA bring-up

HDL verification

Team mentoring

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s or PhD in Electrical Engineering/Signals

Tools

HDL Coder

Git

Job description

Axon seeks a Senior FPGA/RTL Designer to own DSP-friendly FPGA implementations, RTL, and verification for SDR/OFDM modems. You will model in MATLAB/Simulink, generate RTL from Simulink, and ensure timing-closed implementations on Zynq-based platforms. The role blends software, firmware, RF, and hardware teams.

Based in Boston or Scottsdale with a hybrid schedule, you’ll collaborate across departments, mentor engineers, and drive design quality with rigorous verification and documentation.