Senior FPGA Engineers

Kforce Inc; Seattle (WA); On-site; USD 150,000 - 180,000; Full time

Job summary

Kforce Inc is seeking a Mid-Level or Senior FPGA Hardware Design Engineer for a leading engineering technology firm in Seattle. The successful candidate will lead design and verification of FPGA and embedded systems while collaborating closely with cross-functional teams to ensure high performance and quality. This role offers a lucrative salary package along with benefits such as 401K matching and stock options.

Benefits

Comprehensive medical/dental/vision insurance

401(k) with matching

Quarterly bonuses

Paid time off for salaried personnel

Qualifications

• Experience in FPGA design with at least 5-12 years of industry experience.
• Strong understanding of digital design principles.
• Proficiency with Verilog or VHDL HDL programming.

Responsibilities

• Define system-level requirements and develop embedded hardware architecture.
• Perform digital design, capture schematics, and implement PCB layouts.
• Develop hardware test plans and execute verification testing.

Skills

FPGA design

Verilog HDL programming

problem-solving

analytical skills

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

FPGA-based systems such as Lattice or Xilinx

Job description

1 day ago Be among the first 25 applicants

This range is provided by Kforce Inc. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$150,000.00/yr - $180,000.00/yr

Responsibilities

Kforce's client, a rapidly growing engineering technology company is looking for a Mid-Level or Senior FPGA Hardware Design Engineer. This role offers a competitive compensation package, including base salary, quarterly bonuses, 401K matching, stock/RSUs, and more. We are working directly with the hiring manager on this search assignment. Overview: As a Senior FPGA Hardware Design Engineer, you will define system-level requirements, develop embedded hardware architecture, and deliver FPGA and embedded compute implementations. You will be responsible for design, analysis, implementation, and verification of FPGA and embedded processing for electro-mechanical systems, thriving in a fast-paced, hardware-driven environment. You will manage all aspects of FPGA and board-level embedded processor hardware development to deliver product features, system performance, and quality required. This includes independently creating and implementing FPGA architecture using Verilog HDL, conducting simulations, developing testbenches, and performing timing analysis. You will integrate FPGA design with embedded processors and other functional blocks in the system, including designing custom communication interfaces and protocols. Your responsibilities also include performing digital design, capturing schematics, and implementing printed circuit board layouts. You will develop hardware test plans, execute verification testing, and debug designs for board bring-up, troubleshooting, and performance tuning. Maintaining design documentation and test reports is crucial, as is participating in system hardware architecture and design reviews.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Physics, or a related field
• At least 5 years of work experience for Mid-Level position and 8-12+ years of industry experience for a Senior Level position in FPGA design, a strong understanding of digital design principles
• Proficiency with Verilog or VHDL HDL programming
• Experience with FPGA-based systems such as Lattice, Xilinx, or similar, and familiarity with embedded processors and real-time operating systems are essential or similar
• Experience in developing signal processing algorithms, implementing low-level hardware interfaces, and proficiency in scripting languages like Python are required
• Experience developing C/C++ or Python-based libraries for custom hardware is a plus but not required
• Strong understanding of digital design principals and proficiency with Verilog HDL programming, synthesis, and timing closure or similar
• Familiarity with embedded processors and real-time operating systems
• Experience in developing signal processing algorithms is a plus but not required
• Experience with fixed point implementations would be preferred
• Experience implementing low-level hardware interfaces (LVDS, MIPI, SPI, I2C, custom)
• Experience with high-speed differential data interfaces and serial peripheral interfaces
• Excellent problem-solving, analytical, and interpersonal skills are necessary
• Knowledge of RF, Radar or Imaging systems or optics is a plus but not required
  
  

The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.

We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.

Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless and until paid and may be modified in its discretion consistent with the law.

This job is not eligible for bonuses, incentives or commissions.

Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.

By clicking “Apply Today” you agree to receive calls, AI-generated calls, text messages or emails from Kforce and its affiliates, and service providers. Note that if you choose to communicate with Kforce via text messaging the frequency may vary, and message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You will always have the right to cease communicating via text by using key words such as STOP.

Seniority level

• Seniority level

  Associate

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  IT Services and IT Consulting

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