Senior FPGA Engineer: Verilog, SystemVerilog & Debug

VIAVI Solutions; United States; On-site; USD 91,000 - 169,000; Full time

Benefits offered by this job

Paid time off

Health insurance

Life insurance

Disability insurance

401(k)

Bonus program

Job summary

VIAVI Solutions is seeking an experienced FPGA design engineer to join our product development team in the United States. You will design and implement FPGA solutions, write Verilog/VHDL, and tackle complex digital logic for high-speed interfaces.

You will collaborate with software, firmware, and system engineers to integrate FPGA designs, perform simulations, and contribute to design reviews. A strong background in UVM, timing closure, and lab debugging is essential.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering or related field.
• 5+ years of FPGA design and development for commercial products.
• Expertise in VHDL and/or Verilog for complex digital design.
• Strong proficiency with FPGA tools such as Vivado or Quartus.
• Experience with simulation/verification methodologies (UVM, SystemVerilog).

Responsibilities

• Design and implementation of FPGA solutions for new product development.
• Develop Verilog/SystemVerilog code for high-speed interfaces and control logic.
• Perform simulation, synthesis, and place & route for FPGAs.
• Create test benches and verification methodologies for FPGA designs.
• Collaborate with software/firmware engineers to integrate FPGA designs.

Skills

VHDL/Verilog

FPGA design

SystemVerilog/UVM

High-speed design

PCIe/Ethernet

Python scripting

Education

Bachelor's / Master's in EE/CE

Tools

AMD Vivado

Intel Quartus Prime

Job description

VIAVI Solutions is seeking an experienced FPGA design engineer to join our product development team in the United States. You will design and implement FPGA solutions, write Verilog/VHDL, and tackle complex digital logic for high-speed interfaces.

You will collaborate with software, firmware, and system engineers to integrate FPGA designs, perform simulations, and contribute to design reviews. A strong background in UVM, timing closure, and lab debugging is essential.