Senior FPGA Engineer - Lead Digital Design for Space Systems

SEAKR Engineering, Inc.; Englewood, Northern (CO, KY); Hybrid; USD 130,000 - 185,000; Full time

Benefits offered by this job

401(k) retirement plan

Medical, dental, vision insurance

Year-end bonus

Paid leave

Job summary

SEAKR Engineering, Inc. is seeking an experienced FPGA Engineer in Colorado to design digital circuits and state machines for space-grade electronics. The role requires leading small teams and delivering RTL blocks with thorough documentation and code reviews.

Candidates should have extensive FPGA experience (Verilog/VHDL), test benches, and familiarity with multiple RTL languages. The position offers base pay with potential year-end bonus and rich benefits, including medical, dental, vision,

Qualifications

• 10+ years FPGA experience.
• Experience leading small teams.
• Ability to document RTL blocks and participate in reviews.

Responsibilities

• Develop FPGA/ASIC designs using Verilog and/or VHDL.
• Create test benches and simulations for FPGA modules and systems.
• Lead small teams to deliver moderately complex systems according to schedule.

Skills

FPGA design

RTL debugging

Scripting languages

Leadership

Lab bench debugging

Education

Bachelor's degree in Electrical Engineering or Computer Science

Tools

Synplify Pro

ISE

Vivado

Libero

Job description

• Compensation: USD 130000 - USD 185000 - yearly

Company Description

Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space.

Job Description

Seeking an FPGA Engineer who has extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs.

Candidate shall have experience with

• Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexity
• Demonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAs
• FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and Libero
• Scripting languages such as TCL or Python
• Leading small sized teams in order to develop moderately complex systems according to program schedule expectations

Required skills

• FPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design
• Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers

Knowledge of RTL design techniques for radiation upset mitigation and experience using multiple RTL languagesare a plus.

Qualifications

• Candidate shall also have leadership skills and ability to provide support and technical direction to junior engineers.
• Clear written and verbal communication skills are required.
• A Bachelor's degree in Electrical Engineering or Computer Science is desired.
• Must have at least 10+ years of FPGA experience.

Additional Information

Compensation: Base payrange is $130,000-185,000 depending on qualifications. SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan. In addition to base salary, employees are eligible for a year-end bonus. SEAKR offers a variety of paid leave, such as vacation, sick, bereavement, and FMLA.

SEAKR is an Equal Opportunity Employer - All your information will be kept confidential according to EEO guidelines.

Applications will be accepted until 6/19/26

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