Senior FPGA Engineer for Embedded Power Electronics & DSP

Acara Solutions, Inc.

Franksville (WI)

On-site

USD 120,000 - 180,000

Full time

3 days ago
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Job summary

Acara Solutions is seeking a Senior FPGA Engineer to join our client on a full-time direct hire opportunity in Wisconsin. You will design, simulate, and debug FPGA designs using Verilog/VHDL while developing Python tools for FPGA validation and modeling electrical power systems with MATLAB/Simulink.

Collaborating with electrical and controls engineers, you will optimize system performance by integrating digital hardware and embedded software, and perform hardware bring-up and validation using

Qualifications

  • Bachelor's degree in Electrical/Computer Engineering or related field.
  • 5+ years designing FPGA-based embedded systems.
  • Proficiency with Verilog or VHDL and HDL test experience.

Responsibilities

  • Design, simulate, and debug FPGA designs using Verilog and/or VHDL.
  • Develop Python command-line tools and automated test scripts for FPGA validation.
  • Model electrical power systems using MATLAB and Simulink.
  • Optimize system performance by integrating digital hardware and embedded software solutions.
  • Collaborate with electrical and controls engineers to develop advanced power control firmware.
  • Perform hardware bring-up, debugging, and validation using laboratory test equipment.

Skills

Verilog/VHDL
DSP
Embedded systems
Python
Git

Education

Bachelor's degree in EE/CE/CS

Tools

Oscilloscopes
Logic analyzers
Network analyzers
Git

Job description

Acara Solutions is seeking a Senior FPGA Engineer to join our client on a full-time direct hire opportunity in Wisconsin. You will design, simulate, and debug FPGA designs using Verilog/VHDL while developing Python tools for FPGA validation and modeling electrical power systems with MATLAB/Simulink.

Collaborating with electrical and controls engineers, you will optimize system performance by integrating digital hardware and embedded software, and perform hardware bring-up and validation using

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