Senior FPGA Design Engineer

Jet Propulsion Laboratory; La Cañada Flintridge (CA); On-site; USD 152,000 - 187,000; Full time

Job summary

Join a forward-thinking organization as a Senior FPGA Design Engineer, where you will lead innovative projects in radar systems for space exploration. This exciting role involves collaborating with a team of engineers to design and implement cutting-edge signal processing applications that will contribute to groundbreaking missions. With a strong emphasis on creativity and exploration, this position offers the opportunity to work on advanced radar technologies that push the boundaries of science. If you are passionate about engineering and eager to make a lasting impact, this is the perfect opportunity for you.

Benefits

Health Insurance

Dental Insurance

Vision Insurance

Retirement Plans

Paid Time Off

Flexible Schedule

Parental Leave

Childcare Assistance

Learning Opportunities

Rideshare Programs

Qualifications

• 9+ years of experience in FPGA design and digital signal processing.
• Strong background in firmware and software development for telecom applications.
• Proven leadership experience in engineering teams.

Responsibilities

• Lead design and implementation of complex signal processing applications.
• Maintain and improve existing firmware and software for radar systems.
• Provide engineering support for spacecraft mission critical events.

Skills

Digital Signal Processing

FPGA Design

Firmware Development

Software Development

Analytical Skills

Team Leadership

Communication Skills

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Tools

SystemVerilog

VHDL

Verilog

Xilinx Design Tools

Microchip Design Tools

MATLAB

C/C++

Git

Jira

Confluence

Job description

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Senior FPGA Design Engineer

Apply locations JPL Campus time type Full time posted on Posted 30+ Days Ago job requisition id R5138

Job Details

New ideas are all around us, but only a few will change the world. That’s our focus at JPL. We ask the biggest questions, then search the universe for answers—literally. We build upon ideas that have guided generations, then share our discoveries to inspire generations to come. Your mission—your opportunity—is to seek out the answers that bring us one step closer. If you’re driven to discover, create, and inspire something that lasts a lifetime and beyond, you’re ready for JPL.

Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel Mountains and offers a work environment unlike any other: we inspire passion, foster innovation, build collaboration, and reward excellence.

The Radar Science and Engineering Section in the Communications, Tracking, and Radar Division conducts research, development, and flight missions in the field of airborne and spaceborne remote sensing radar for NASA and other government agencies. This section specializes in systems and techniques related to synthetic aperture radar (SAR) imaging, radar interferometry, altimetry, Earth and planetary subsurface sounders, scatterometry, and cloud and precipitation radars. The section is also a leader in the area of planetary landing radars. Our radar program focuses on Earth and planetary science missions, with emphasis on first-of-a-kind radar systems and cutting-edge technology.

Responsibilities

We invite you to join the Radar Science and Engineering Section (334). You will report to the Radar Section Management Team and the Group Supervisor of the Radar Digital Systems Group. We are seeking a Field Programmable Gate Array (FPGA) Engineer IV, responsible for the design and implementation of digital subsystems for spaceborne and airborne Radar Systems and their Engineering Ground Support Equipment (EGSE). In this role you will lead a team of engineers responsible for radar architecture, firmware, hardware, and software, participate in new technologies definition and development, and be a key member of spaceborne and airborne Earth Science and Planetary exploration missions that include Radar systems developed at JPL.

The Radar Section is currently developing radars for the NASA Venus Veritas mission, the European Space Agency Venus EnVision mission, airborne synthetic aperture radar (SAR) systems operated from aircraft (AIRSAR-NG) and drones (TREx), and performing formulation and technology development tasks in support of decadal survey missions including Surface Topography and Vegetation (STV), Surface Deformation and Change (SDC), and Aerosol and Cloud, Convection and Precipitation (ACCP).

The radars for spaceborne missions use radiation-hardened (e.g., Virtex-5QV) and radiation-tolerant (e.g., Kintex UltraScale) FPGAs, while the airborne systems use RFSoC devices in SOSA-compliant VPX form-factors. Technology development efforts include real-time backprojection on Versal AI Engines, radar processing on the new Microchip High-Performance Spaceflight Computer (HPSC), and collaboration with experts across JPL.

What You Will Do

• Lead teams of firmware and hardware software engineers, and collaborate with system engineers, to design and implement highly complex signal processing applications through all phases of a project, from conception, design, implementation, test, and deployment.
• Maintain (and improve) existing firmware and software for radar digital subsystems.
• Provide engineering support to Radar Operations: support spacecraft mission critical events and interface compatibility testing; monitor operational subsystem performance; assist Radar Operations with performance issues and participate in subsystem troubleshooting.
• Define, develop, and document subsystem requirements, designs, and test procedures.
• Review/update/maintain hardware and software interface agreements.
• Lead engineering teams to prepare and present materials at task design reviews and delivery reviews.

Requirements

• A Bachelor’s degree in Electrical Engineering or related disciplines with a minimum of 9 years of related experience; or a Master’s degree in similar disciplines with a minimum of 7 years of related experience; or PhD in similar disciplines with a minimum of 5 years of related experience.
• Strong knowledge and background in digital signal processing, modulation and demodulation schemes, telemetry encoding and decoding techniques.
• Experience developing firmware and software for signal processing or telecom applications.
• Analytical and debugging skills.
• Effective communication skills, both written and verbal.
• Experience leading a team of hardware, firmware, software, or test engineers.
• Mastery of any one of the following: SystemVerilog, VHDL, Verilog.
• Experience with FPGA synthesis and simulation tools.

Preferred Skills

• Experience with Xilinx devices and associated design tools, particularly: Versal, RFSoC, MPSoC, Kintex UltraScale, Virtex-5, Vivado, Vitis, PetaLinux, ISE.
• Experience with Microchip FPGA devices and associated design tools, particularly: PolarFire, ProASIC3, RTAX, Libero IDE/SoC.
• Experience with RFSoC or MPSoC platforms from Real Digital, Pentek, VadaTech, or AlphaData.
• Experience with 3U or 6U VPX hardware and associated standards, interfaces, and protocols: OpenVPX, SpaceVPX, SOSA, PCIe, IPMI.
• Experience with full-stack firmware and embedded software development on SoC.
• Experience selecting, evaluating, and interfacing to multi-gigabit DACs and ADCs.
• Experience with UVM, regression testing, and automated testing for FPGA verification.
• Experience with Ethernet (including optical variants) from physical layer (e.g., FW implementation of PHY/MAC) through application layer (e.g., sockets programming).
• Knowledge and experience with MATLAB, C/C++, Python.
• Experience using git and GitHub to manage a code base during development.
• Experience with continuous integration tools (e.g., Jenkins).
• Experience with project collaboration and management tools: Confluence, Jira, Microsoft Project.
• Extensive experience designing and/or verifying digital systems for high reliability applications.
• Thorough understanding of instrument development and testing, from component level to system level.
• Broad knowledge of industry practices and standards across a range of applications related to digital systems, hardware, and software engineering.
• Demonstrated ability to interact productively and proactively with system and instrument engineers.
• Strong communication skills, interpersonal skills, and ability to manage projects on schedule and within allocated resources.
• Strong organizational and project management skills, including schedule and budget management.
• Ability to work on multiple projects in parallel.

Closing Statement

We are an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. JPL is a VEVRAA Federal Contractor. For more information about "EEO is the Law" click here: http://www.eeoc.gov/employers/upload/eeoc_self_print_poster.pdf

The Jet Propulsion Laboratory is a federal facility. Due to rules imposed by NASA, JPL will not accept applications from citizens of designated countries unless they are Legal Permanent Residents of the U.S or have other protected status under 8 U.S.C. 1324b(a)(3). The Designated Countries List is available at http://oiir.hq.nasa.gov/nasaecp/

JPL has a catalog of benefits and perks that span from the traditional to the unique. This includes a variety of health, dental, vision, wellbeing, and retirement plans, paid time off, learning, rideshare, childcare, flexible schedule, parental leave and many more. Our focus is on work-life balance, and living healthy, fulfilling lives as we Dare Mighty Things Together. For benefits eligible positions, benefits are effective the first day of the month coincident with or immediately following the employee’s start date.

For further benefits information click Benefits and Perks

The hiring range displayed below is specifically for those who will work in or reside in the location listed. In extending an offer, Jet Propulsion Laboratory considers factors including, but not limited to, the candidate’s job related skills, experience, knowledge, and relevant education/training. Hiring range for this job may be adjusted based on primary work location outside of Pasadena, California. This adjusted range will be provided to candidates by the Recruiter when applicable.

The typical full time equivalent annual hiring range for this job in Pasadena, California.

$152,672 - $186,368

JPL is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to sex, race, color, religion, national origin, citizenship, ancestry, age, marital status, physical or mental disability, medical condition, genetic information, pregnancy or perceived pregnancy, gender, gender identity, gender expression, sexual orientation, protected military or veteran status or any other characteristic or condition protected by Federal, state or local law.

In addition, JPL is a VEVRAA Federal Contractor.

EEO is the Law.

EEO is the Law Supplement

Pay Transparency Nondiscrimination Provision

The Jet Propulsion Laboratory is a federal facility. Due to rules imposed by NASA, JPL will not accept applications from citizens of designated countries or those born in a designated country unless they are U.S. Citizens, Legal Permanent Residents of the U.S or have other protected status under 8 U.S.C. 1324b(a)(3). The Designated Countries List is available here.