Senior FPGA Design Engineer

GCS Recruitment; Dallas (TX); On-site; USD 120,000 - 190,000; Full time

Job summary

Unknown is seeking a Senior FPGA Design Engineer to own programmable logic in the phased-array signal chain for space-grade hardware. The role focuses on high-speed datapaths, multi-gigabit link configuration, and bringing up new boards in a lab with the electronics team.

You will work with 25G/50G/100G SERDES, MRMAC/GTY blocks, and embedded Linux on Versal ACAP, delivering real hardware for flight applications with hands-on design and validation on first-article boards.

Qualifications

• 8+ years of RTL design (Verilog/SystemVerilog/VHDL) shipped in real products.
• Experience bringing up 25G/50G/100G links on real hardware.
• Working knowledge of Versal ACAP architecture and toolchain.

Responsibilities

• Design, integrate, and debug RTL for high-speed datapaths on Versal devices.
• Configure and bring up GTY transceivers and supervise 25G/50G/100G links.
• Build and validate embedded Linux images, device trees, and drivers for the processing system.

Skills

High-speed interfaces

MRMAC/GTY

Versal ACAP

Embedded Linux

Tools

Vivado/Vitis

Job description

Job Title: Senior FPGA Design Engineer

About The Program:

Our client is building one of the world's largest low-Earth-orbit satellite constellations, delivering broadband internet from space. The hardware team behind it designs the electronics that drive the satellites' phased-array antennas: meter-scale, 20+ layer boards carrying custom silicon connected by ~25 Gbps high-speed serial links. Boards are designed, brought up, and validated in-house - engineers on this team see their own work running on real flight hardware.

The Role:

You will own programmable logic in the phased-array signal chain on AMD/Xilinx Versal devices - designing and integrating high-rate datapaths between the board's custom silicon, configuring and debugging multi-gigabit transceiver links, and bringing your logic up on brand-new boards in the lab alongside the electrical engineering team. This is a hands-on design-and-hardware seat: your deliverables run on real boards headed for orbit, not in a simulation environment.

What You'll Do:

• Design, integrate, and debug RTL for high-speed datapaths on Versal ACAP devices.
• Configure and bring up GTY transceivers - link tuning, eye scans, and debug of live 25 Gbps-class serial links.
• Configure MRMAC hard IP for multi-rate Ethernet (25G / 50G / 100G) and validate high-rate traffic end to end.
• Build and maintain embedded Linux (PetaLinux/Yocto) images, device trees, and drivers for the Versal processing system.
• Bring up your logic on first-article boards in the lab - JTAG, ILA, and bench instrumentation - working shoulder to shoulder with board design engineers.
• Build debug and monitoring hooks used across design validation campaigns.

Required Experience:

• 25G/50G/100G - Very high speed interfaces - hands-on design and bring-up at 25G / 50G / 100G.
• MRMAC & GTY - Direct experience configuring MRMAC and GTY blocks - transceiver setup, tuning, and link debug on real hardware.
• Versal ACAP - Working knowledge of the Versal ACAP architecture and toolchain (Vivado/Vitis).
• Embedded Linux - Building images, device trees, and drivers for ARM-based FPGA processing systems (PetaLinux/Yocto).
• 8+ years of RTL design (Verilog/SystemVerilog/VHDL) shipped in real products, with timing closure on modern devices and genuine board bring-up experience.

Nice To Have:

• JESD204, Aurora, or other high-speed converter/serial protocols.
• Aerospace or high-reliability design exposure (DO-254, MIL-STD, radiation-aware design).
• Prior satellite, SATCOM, radar, or high-speed networking product work.
• Experience prototyping functions ahead of custom ASIC development.