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Pratt & Whitney seeks an experienced ASIC/FPGA design engineer to drive digital architecture, RTL development, and verification for airborne hardware. You will create RTL in VHDL/Verilog/SystemVerilog, build verification testbenches, and craft timing constraints while collaborating with cross‑functional teams on instrumented projects.
You will exploit FPGA toolchains (Questasim, Vivado, Libero, Synplify Pro), perform synthesis, timing analysis, and carry out DO-254 processes for AEH.
Pratt & Whitney seeks an experienced ASIC/FPGA design engineer to drive digital architecture, RTL development, and verification for airborne hardware. You will create RTL in VHDL/Verilog/SystemVerilog, build verification testbenches, and craft timing constraints while collaborating with cross‑functional teams on instrumented projects.
You will exploit FPGA toolchains (Questasim, Vivado, Libero, Synplify Pro), perform synthesis, timing analysis, and carry out DO-254 processes for AEH.