Senior Foundry Interface Engineer - Yield Optimization

SiTime Corp.; Santa Clara (CA); Presencial; USD 148.000 - 204.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

401k plan

Health, dental, vision, life insurance

Parental leave

Equity grants

Time off plans

Descripción de la vacante

SiTime Corp. is seeking a senior yield engineering leader to support Foundry interfaces and drive wafer yield improvements. You will lead projects, mentor teams, and coordinate with foundries to ensure timely wafer release and continuous process optimization.

The role requires deep semiconductor process knowledge, leadership, and strong communication skills to manage multiple complex projects in a fast-paced environment.

Formación

• Master's degree with 13+ years of experience or PhD with 10+ years in semiconductor process/wafer yield fields.
• English proficiency in a professional business environment.
• Proven track record in yield Pareto construction, modeling, projection and long-term yield roadmaps.
• Experience with PDF Exensio or other Big Data Analysis tools.
• Extensive experience collaborating with foundries and porting between fabs.
• Deep knowledge of inline inspection methods, SORT programs and device reliability.
• Strong leadership and ability to set standards and drive to targets.
• Excellent written and verbal communication with multi-project management.

Responsabilidades

• Lead Foundry yield improvement and mitigate yield detractors.
• Manage foundry yield excursions and implement Continuous Improvement Plan.
• Oversee safe launch for foundry processes.
• Provide technical guidance on Fab transfer projects.
• Direct wafer lot progress, DOE strategies and process skew splits during development.
• Support device performance analysis for mixed-signal devices.
• Ensure compliance with fab yield metrics and E-test processes.
• Communicate process health to stakeholders and drive on-time wafer release from fab.
• Leverage AI/ML predictive modeling to improve test-chip yield projection.
• Coordinate with foundries to resolve critical escalations and drive continuous improvement.

Conocimientos

English proficiency

Leadership

Communication

Project management

Educación

Master's degree + 13+ years OR PhD + 10+ years in semiconductor/physical science

Herramientas

PDF Exensio

Descripción del empleo

SiTime Corp. is seeking a senior yield engineering leader to support Foundry interfaces and drive wafer yield improvements. You will lead projects, mentor teams, and coordinate with foundries to ensure timely wafer release and continuous process optimization.

The role requires deep semiconductor process knowledge, leadership, and strong communication skills to manage multiple complex projects in a fast-paced environment.