Senior Formal Verification Engineer - Modem SoC (AI-Driven)

Amazon; Austin (TX); On-site; USD 185,000 - 250,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a Senior Formal Verification Engineer to lead formal verification across modem SoC designs, applying rigorous mathematical methods to prove design correctness and uncover corner-case bugs. You will mentor engineers, collaborate with RTL, DV, emulation teams, and drive formal methods across tape-outs.

The role emphasizes a formal-first mindset, reusable verification infrastructure, and integration of AI-centric verification techniques to

Qualifications

• 8+ years of ASIC/SoC design verification with a strong focus on formal verification.
• Experience with JasperGold and/or Questa Formal.
• Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification.
• Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis.
• Ability to drive proof convergence on complex designs using abstraction, case-splitting, and assume-guarantee techniques.
• Proficiency in SystemVerilog and UVM concepts.
• Experience leveraging AI/LLM tools to accelerate formal verification workflows.

Responsibilities

• Develop and execute formal verification strategies using JasperGold and/or Questa Formal for property checking (FPV), connectivity checking (CC), register verification, and sequential equivalence checking (SEQ).
• Write, review, and debug SystemVerilog Assertions (SVA) — including assumptions, assertions, and cover properties.
• Drive convergence on formal proofs by applying abstraction techniques and assume-guarantee reasoning.
• Collaborate with RTL designers, architects, and DV engineers to define verification plans that integrate formal methods with UVM-based simulation and emulation.
• Champion a formal-first verification strategy across SoC and NoC partitions.
• Develop reusable formal verification infrastructure, including constraint libraries and property templates, integrated into CI/CD regression.
• Contribute to coverage closure strategies by leveraging formal coverage analysis to complement simulation-based coverage.
• Mentor DV engineers in formal verification techniques, SVA best practices, and proof convergence.
• Partner with EDA vendors to evaluate new formal verification capabilities and drive tool improvements.

Skills

Formal verification

SystemVerilog Assertions

AI/LLM tooling

Proof convergence

CI/CD pipelines

Education

Bachelor's degree in electrical/computer engineering or equivalent

Tools

JasperGold

Questa Formal

SystemVerilog

UVM

Python

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a Senior Formal Verification Engineer to lead formal verification across modem SoC designs, applying rigorous mathematical methods to prove design correctness and uncover corner-case bugs. You will mentor engineers, collaborate with RTL, DV, emulation teams, and drive formal methods across tape-outs.

The role emphasizes a formal-first mindset, reusable verification infrastructure, and integration of AI-centric verification techniques to