Senior Formal Verification Engineer for SoC & NoC ASICs

Etched; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical/dental/vision

Housing subsidy

Relocation support

Wellness benefits

Daily lunch

Job summary

Etched is seeking a Formal Verification Engineer to join our ASIC Design Verification team in Silicon Valley. You will drive formal verification across custom IP, interface IP, and SoC subsystems powering our ASICs, collaborating with architects, RTL designers, DV engineers, emulation, and software/firmware to prove design correctness and uncover deep corner-case bugs.

You will translate design intent into high‑value formal properties, contribute to sign‑off methodology, and work with

Qualifications

• 5+ years in design verification of complex digital silicon.
• Strong SystemVerilog and formal methods knowledge.
• Experience with commercial formal tools and methodologies.

Responsibilities

• Define and drive formal verification strategy for ASIC DV team.
• Develop formal plans covering functional correctness and deadlock freedom.
• Build reusable formal environments using SVAs and reference models.
• Drive proof convergence and closure criteria with rigorous coverage metrics.
• Collaborate with architects, RTL designers, DV, emulation, and software teams.

Skills

5+ years exp

SystemVerilog

SV Assertions

SoC architectures

RTL debugging

Python scripting

Tools

Cadence JasperGold

Synopsys VC Formal

Siemens Questa Formal

Job description

Etched is seeking a Formal Verification Engineer to join our ASIC Design Verification team in Silicon Valley. You will drive formal verification across custom IP, interface IP, and SoC subsystems powering our ASICs, collaborating with architects, RTL designers, DV engineers, emulation, and software/firmware to prove design correctness and uncover deep corner-case bugs.

You will translate design intent into high‑value formal properties, contribute to sign‑off methodology, and work with