Senior Emulation Performance & Debug Architect

Nutanix; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks a Senior Emulation Performance Methodology & Debug Engineer to lead emulation framework development and cross-team debug for SoC pre-silicon platforms.

You will work with FPGA prototyping, Veloce/Palladium tools, Verilog/SystemVerilog, and scripting in Python/TCL to create uniform methodologies, enable bring-up, and resolve low-level hardware/software issues.

Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design/verification/validation/integration experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design/verification/validation/integration experience.
• PhD in Science, Engineering, or related field and 0+ years of ASIC design/verification/validation/integration experience.

Responsibilities

• Design, development, and deployment of emulation build generation and debug strategies.
• Pre-silicon prototyping and bring-up of FPGA emulation hardware/software.
• Debugging low-level software and hardware issues using JTAG and kernel debuggers.
• Collaborate cross-site with vendors and internal teams to improve emulation methodologies.
• Validate and debug digital circuits and SoC building blocks (PMIC, NoC, peripherals).

Skills

Verilog/SystemVerilog

C programming

Python

TCL

FPGA Prototyping

Veloce

Palladium

Synthesis

Place and Route

Clocking

Timing Closure

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Verilog/SystemVerilog tools

FPGA toolchains

JTAG

Kernel debuggers

Job description

Qualcomm Technologies, Inc. seeks a Senior Emulation Performance Methodology & Debug Engineer to lead emulation framework development and cross-team debug for SoC pre-silicon platforms.

You will work with FPGA prototyping, Veloce/Palladium tools, Verilog/SystemVerilog, and scripting in Python/TCL to create uniform methodologies, enable bring-up, and resolve low-level hardware/software issues.