Senior Digital Verification Engineer — Chiplet & Ethernet

OpenTalent; California (MO); On-site; USD 130,000 - 180,000; Full time

Job summary

OpenTalent is seeking an Eliyan staff digital verification engineer to join a fast-paced chiplet startup building high-performance, manufacturable products. You will design state-of-the-art testbenches and chip-level test cases for PHYs and controllers, collaborating with a cross-functional team from concept to CI/CD ready releases.

Ideal candidates hold a Masters or PhD in Electrical Engineering with 6+ years of verification experience, deep SystemVerilog/UVM skills, and hands-on Ethernet

Qualifications

• Masters or Ph.D in Electrical Engineering with 6+ years of experience.
• Hands-on verification of serial transmission protocols (Ethernet 100G+).
• Strong SystemVerilog/UVM knowledge and test environment expertise.

Responsibilities

• Develop and execute verification plans for connectivity IPs and Chiplets.
• Create and maintain SystemVerilog/UVM-based verification environments.
• Write and debug SystemVerilog/UVM compliant test cases for block and chip level.
• Maintain a regression environment for design CI/CD pipelines.
• Collaborate with design engineers to ensure design quality with reviews.
• Lead junior verification engineers and coordinate VIPs integration.

Skills

UVM expertise

SystemVerilog

Verification planning

Leadership

Education

Master's or PhD in Electrical Engineering

Tools

Regression management tools

Coverage analysis tools

Job description

OpenTalent is seeking an Eliyan staff digital verification engineer to join a fast-paced chiplet startup building high-performance, manufacturable products. You will design state-of-the-art testbenches and chip-level test cases for PHYs and controllers, collaborating with a cross-functional team from concept to CI/CD ready releases.

Ideal candidates hold a Masters or PhD in Electrical Engineering with 6+ years of verification experience, deep SystemVerilog/UVM skills, and hands-on Ethernet