Senior Digital & SerDes Integration Engineer

NXP Semiconductors; San Jose (CA); On-site; USD 166,200 - 228,500; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

401(k)

Paid leave

Job summary

NXP Semiconductors in San Jose is looking for a Senior Digital/AMS Design Engineer to drive complex integration tasks in Automotive SerDes transceivers. Responsibilities include RTL design, timing closure, and silicon validation. Candidates should possess a BSEE/MSEE with 5–8 years of experience in digital design, expertise in SystemVerilog/Verilog, and familiarity with high-speed interfaces. The competitive salary range is $166,200 to $228,500 annually, alongside comprehensive company benefits and a commitment to equal opportunity.

Qualifications

• 5–8+ years of experience in Digital RTL Design or Digital Integration.
• Advanced proficiency in SystemVerilog/Verilog for synthesis.
• Strong understanding of Static Timing Analysis and clock domain crossing.

Responsibilities

• Develop and integrate RTL for control loops, calibration engines, and data paths.
• Define and implement digital interfaces for analog blocks.
• Lead the digital implementation flow and achieve timing closure.

Skills

Digital RTL Design

SystemVerilog/Verilog

Python

Static Timing Analysis

Digital Integration

Education

BSEE/MSEE

Tools

Logic Analyzers

High-speed scopes

JTAG/I2C/SPI protocols

Job description

NXP Semiconductors in San Jose is looking for a Senior Digital/AMS Design Engineer to drive complex integration tasks in Automotive SerDes transceivers. Responsibilities include RTL design, timing closure, and silicon validation. Candidates should possess a BSEE/MSEE with 5–8 years of experience in digital design, expertise in SystemVerilog/Verilog, and familiarity with high-speed interfaces. The competitive salary range is $166,200 to $228,500 annually, alongside comprehensive company benefits and a commitment to equal opportunity.